Zynq UART Baud Rate Limit and IP Cores

[e219522eee]

Hi,

I'm trying to design a system which has to communicate with 4,125,000 bps (~4 Mbps) UART baud rate. I could not realize a Zynq model which has a processor supporting this UART requirement.

I also investigated some IP Cores for FPGA part of Zynq which promotes 4 Mbps however i could not find again. My question is that is there a limit of baud rate on Zynq models and if it is, is it possible to write a UART Vhdl code, which supports this baud rate?

My another question is about AXI protocol. Is there a baudrate limit about AXI on Zynq?

Thank you.

[u4223374 · Accepted solution]

There is a limit for the PS-PL AXI ports, but it's high - 250MHz 32-bit for the general-purpose interfaces and 250MHz 64-bit for the high-performance ones. This is not going to be the limiting factor for your UART.

You should definitely be able to write a UART operating at 4.125MHz in VHDL or Verilog. Even with a very simple clock divider, you can get to 4.166MHz by dividing a 100MHz clock by 24 - and this results in a clock error of about 1%. UARTs can normally tolerate 5% easily, so 1% should be fine.

Obviously signal quality may be an issue if you're doing this over long distances, but for short range it'll be fine.

[e219522eee]

I need to configure this UART communication with an error that must be less than 10^(-8). Can both 4Mbs baud rate and this error rate be obtained, in your opinion?

[annosauer1]

I am new to the ZYNQ, but I am  a HW EE

To your question...

It depends very much on the line driver you are using.

For instance RS422 can do 4Mbit  easy but RS232 probably no more than a few foot of cable length.

KB

[e219522eee]

My interface is RS485 so i think it will be possible. Thank you.

[bbawkon]

4,125,000 bps should be no problem using an AXI_UART (not lite) and a good RS-422/RS-485 transceiver.

I do a similar speed for a custom sensing application.

If it were me, I would clock the AXI bus at 66MHZ (66,000,000), hang an AXI_UART on the AXI Bus, and then set the MSB:LSB Baud rate divider to 1.  That will give you 66,000,000 / 16 / 1 = 4,125,000

I don't have Vivado on the machine I'm writing this on, but I think you'll need to do one of two things in order to clock the AXI Bus at 66,000,000

A) Use a Clock Wiz to generate that freq.

B) Use an external oscillator (probably what I would do) and bring it in to a clock capable I/O pin.  Use that clock to drive the AXI bus clock.

Good luck with your design,

Ben

[songze_z]

Can you tell me the full name of the "AXI UART"?

Is that an IP core?

I only find AXI_UARTLite and AXI Uart16550.

Thanks