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Registered: ‎11-01-2016

Zynq US+ MIO Pin Assigns Split

I am working on a new design based on Zynq Ultrascale+ ZU03

I am trying to use as many built in PS-IO as I can.

I see that for some functions I am not using all of the pins in a group and I want to know if I can use unused pins within a group as OTHER MIO functions.


For example I have MIO pins 13-25 mapped to SD0 (13pins)
But I am wiring this to a WiFi device that will only use 6 pins. Pins 13,14,15,16,21,22
Can I use the remaining 7 pins (17,18,19,20,23,24,25) in that group for something else like I2C/CAN ports etc?


UG1085 says I can't split a function across two groups, but doesn't explain what I can do.  The multiplexers look like this should be do-able.

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Community Manager
Community Manager
Registered: ‎07-23-2012

I think you are referring to the below comment in UG1085-
"The routing of the IOP interface I/O signals must be done as a group; that is, the signals must not be split and routed to different MIO pin groups. For example, if the SPI 0 CLK is routed to MIO pin 40, then the other signals of the SPI 0 interface must be routed to MIO pins 41 to 45."

It says that if we are lock one of the pins of controller to a MIO pin then the remaining pins of that peripheral should be LOCed sequentially.

In your case, since your Wifi peripheral requires only 6 pins, you can use the remaining pins for different peripherals.
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