Zynq UltraScale+ MPSoc Version 3.1 PL to PS interrupts

[fgotwald]

The IP comes with these 2 parameters:

PSU__NUM_F2P0__INTR__INPUTS == 2

PSU__NUM_F2P1__INTR__INPUTS == 1

while the Technical Reference Manual states:

"Except for IRQ(121) through IRQ(128) and IRQ(136) through IRQ(144), which are the interrupts from the PL,"

Shouldn't the IP have been released with the above 2 parameters set to 8?

[fgotwald]

Here's a example recipe to see the 16 PL to PS interrupts. Exact filenames may differ.

1) Quit vivado

2) Edit these 3 files and change the 2 parameters to 8:

<project>.srcs/sources_1/bd/design_1/design_1.bd

<project>.srcs/sources_1/bd/design_1/hw_handoff/design_1.hwh

<project>.srcs/sources_1/bd/design_1/ip/design_1_zynq_ultra_ps_e_0_0/design_1_synq_ultra_ps_e_0_0.xci

3) Start vivado, open block diagram. The zynq ultra will complain that the IP is out of date. Update it.

4) Now note the 8 inputs available on the zynq block for IRQ0 and IRQ1 (if you have them enabled in the zynq block config).

[jg_bds]

Looks like another 2017.3 snafu.  I assume you're also getting this warning:

The width of the ps_pl_irqN[0:0] port(s) should be updated automatically with the attached bus, when the block diagram products are generated.

However, 2017.3 (V3.1), bad:

Instead of 2017.2 (V3.0) good:

If reverting back to 2017.2 isn't an option, it looks like you might need to continue hacking the output products.

-Joe G.

[kinkeads]

I'm seeing the same issue in 2017.3.   PL_PS_IRQ0 auto-sizes up to 8-bits, but PL_PS_IRQ1 has a max width of only 4 bits.  I edited the three files suggested by the OP and all 8-bits are now available on IRQ1.  I fear my edits will be overwritten by Vivado if I make a change to the PS.

[jg_bds]

I think I recently ran a trial design in 2017.3.1--with the new update.  And I'm pretty sure that version correctly handled the interrupt port auto-adjustment.

-Joe G.

[ritakur]

This a known issue. please try the following solution or delete the old PS8 instance then add a new one

https://www.xilinx.com/support/answers/69960.html