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Observer
Observer
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Registered: ‎09-05-2018

Zynq Ultrascale+ 3EG xemacps_example_intr_dma example fails

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Hi,

I have an Avnet UltraZed board and created a basic design, using GEM3.

I have created a LWIP UDP application to test the ethernet connectivity. In this case everything works fine and I can valid packets on the wire.

However.

I have used xemacps_example_intr_dma.c example source code, to repeate the same types of tests, using bare metal.

I am unable to get the xemacps_example_intr_dma example to transmit anything on the wire, and there are no interrupts generated. This includes with and without enabling loop back mode.

 

I can only assume that there is some slight difference between the way the LWIP port sets up a tx buffer descriptor and the way the xemacps_example_intr_dma sets up the descriptor that is causing the EMAC not to transmit.

I found one additional block of code in the LWIP, that is not in the xemacps_example_intr_dma. However it makes no difference to the outcomes.

dmacrreg = XEmacPs_ReadReg(sZYNQ_EMAC.pEMAC.Config.BaseAddress, XEMACPS_DMACR_OFFSET);
dmacrreg = dmacrreg | (0x00000010);
XEmacPs_WriteReg(sZYNQ_EMAC.pEMAC.Config.BaseAddress, XEMACPS_DMACR_OFFSET, dmacrreg);

 

Does anyone know the state of the xemacps_example_intr_dma example. Does it work on Ultrascale GEM's? 

 

Thanks

 

 

 

 

 

 

 

 

 

 

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Observer
Observer
486 Views
Registered: ‎09-05-2018

I seem to have resolved the issue using the below snipped of code for anyone else that has similar problems.

 

// https://www.xilinx.com/support/answers/63776.html
XScuGic_CPUWriteReg(pGIC, XSCUGIC_EOI_OFFSET, XPS_XXX_INT_ID);

View solution in original post

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Observer
Observer
579 Views
Registered: ‎09-05-2018

Some further information.

 

As mentioned the LWIP UDP Performance example works well, but I've discovered it only works well once, it will not work if downloaded again on the hardware.

If I re-program the FPGA (without powering down the board) and download the LWIP example again, the same problem occurs, the example will not run.

 

However if I power off the hardware, then re-program the FPGA the example will run.

 

I get the feeling this may have something to do with the DP83867 PHY.  As a measure, I am doing a software reset on the PHY, however this has no effect on only being able to run the examples once without requiring power on.

 

Any Suggestions?

Thanks.

 

 

 

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Moderator
Moderator
560 Views
Registered: ‎07-31-2012

Hi @safetylok ,

I dont see this issue on ZCU102 board with this xemacps_example_intr_dma application.

This is loopback mode application and works fine at my end.

 

Regards

Praveen


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Observer
Observer
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Registered: ‎09-05-2018

Hi @pvenugo 

 

Thanks for taking the time to look at this issue. 

 

The problem still exists on both the xemacps_example_intr_dma example and the LWIP example application on the Avnet UltraZed board.

 

I have found a quicker work around, and that is to press the reset button, re-program the FPGA and re-download the application. I can only assume this has something to do with external hardware (like the PHY) because I can't imagine the PS side of things locking up.

 

Thanks.

 

 

 

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Highlighted
Observer
Observer
487 Views
Registered: ‎09-05-2018

I seem to have resolved the issue using the below snipped of code for anyone else that has similar problems.

 

// https://www.xilinx.com/support/answers/63776.html
XScuGic_CPUWriteReg(pGIC, XSCUGIC_EOI_OFFSET, XPS_XXX_INT_ID);

View solution in original post

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