11-29-2018 10:26 AM
In our custom board with XCZU6CG-2FFVC900I device, we are facing an issue with DDR4 initialization. The memory interface is x64 (Micron MT40A512M16JY-083E-IT) with ECC. The initialization fails when we generate the Vivado project with or without ECC. Please find the IP settings below.
When we try to launch the FSBL from SDK, it gets stuck in psu_init.tcl. With further debug prints, we could find out that it was getting stuck at the following stage:
#trigger PHY training
poll 0xFD080030 0x00000FFF 0x00000FFF
The expected data from PGSR0 is 0xFFF but what we are getting is 0x80C000FF indicating a write levelling adjustment error and a DQS gate training error.
We tried to read out the debug registers in the error condition and found the following observations:
As per the above readings, a write levelling error is not present in any of the byte groups. But the PGSR0 still shows that one is present.
For DQS gate training, it shows a read levelling error status on all the byte groups. DGSL field is showing a value of 31 but the valid range is only till 18. We have confirmed that before the initialization is triggered, DGSL is at 0. We tried changing the value of DGSL prior to triggering the initialization, but it is still getting reverted back to the same value.
Please suggest next steps. Any help would be greatly appreciated.
11-30-2018 07:39 AM
I suggest that you first try with a supported memory model by vivado. I think the MT40A256M is supported with compatible timings. See if that works.
Then, you'll modify the setting accordingly.
12-01-2018 06:39 AM
We tried modifying the file settings for MT40A256M but ended up with the same error. Do you have any screenshot of the working config to confirm if we are putting the right values?
12-03-2018 08:38 AM
There is no file to configure. You open your BD, and reconfigure the zynq in the IP integrator.
At this stage, you can go to the PS DDR controller panel and select the memory preset instead of the custom one.
05-20-2019 07:38 PM
Hi, I have a same issue in our board. Our FPGA is XCZU9CG with MT40A512M16LY-062Ex2 (32bit)
We follow PG201 December 5, 2018 page 38 use preset config (MT40A256M16GE 083E), and modified as below, but we got same error 0xFD080030: 80C000FF. We don't know how to modify the correct config for our board. Anyone know how to do?
05-28-2019 02:01 PM
Since you are debugging a different issue, would you be willing to create a new forum post with your information? That will allow it to be more easily seen by the appropriate source of help.
06-10-2020 04:50 AM - edited 06-10-2020 04:52 AM
Lot of time left, but still. Did you solve your problem with memory cause i have the same issue on my custom board and maybe you can give me some advise
07-27-2020 03:49 AM
07-27-2020 04:21 AM - edited 07-27-2020 04:22 AM