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Visitor
Visitor
2,110 Views
Registered: ‎07-16-2018

Zynq Ultrascale+ PSDDR | DDR4 initialization error with psu_init.tcl

Hi, 

In our custom board with XCZU6CG-2FFVC900I device, we are facing an issue with DDR4 initialization. The memory interface is x64 (Micron MT40A512M16JY-083E-IT) with ECC. The initialization fails when we generate the Vivado project with or without ECC. Please find the IP settings below.ddr_controller_config1.JPG

 

ddr_controller_config2.JPG

 

 

 


When we try to launch the FSBL from SDK, it gets stuck in psu_init.tcl. With further debug prints, we could find out that it was getting stuck at the following stage:

#trigger PHY training
poll 0xFD080030 0x00000FFF 0x00000FFF

 

The expected data from PGSR0 is 0xFFF but what we are getting is 0x80C000FF indicating a write levelling adjustment error and a DQS gate training error.
We tried to read out the debug registers in the error condition and found the following observations:

 WLERRWLDONEWLPRDWLDWDQDWDQSLWLSL
DX00111705702
DX10111505702
DX20111905702
DX30111505802
DX40111305702
DX50111505702
DX60111505702
DX70111305802
DX80111705702

 

As per the above readings, a write levelling error is not present in any of the byte groups. But the PGSR0 still shows that one is present. 

 

 RDLVLERRGDQSPRDDGSLDQSGD
DX0111431105
DX1111731109
DX2111631109
DX3111531107
DX4111531107
DX5111531107
DX6111531107
DX7111531107
DX8111631107

 

For DQS gate training, it shows a read levelling error status on all the byte groups. DGSL field is showing a value of 31 but the valid range is only till 18. We have confirmed that before the initialization is triggered, DGSL is at 0. We tried changing the value of DGSL prior to triggering the initialization, but it is still getting reverted back to the same value.

Please suggest next steps. Any help would be greatly appreciated.

Thanks,

Mohan

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10 Replies
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Voyager
Voyager
2,086 Views
Registered: ‎03-17-2011

Hi

I suggest that you first try with a supported memory model by vivado. I think the MT40A256M is supported with compatible timings. See if that works.

Then, you'll modify the setting accordingly.

Regards,

 

--Sebastien
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Visitor
Visitor
2,064 Views
Registered: ‎07-16-2018

Hi Sebastien,

We tried modifying the file settings for MT40A256M but ended up with the same error. Do you have any screenshot of the working config to confirm if we are putting the right values?

 

Thanks,

Mohan

 

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Voyager
Voyager
2,037 Views
Registered: ‎03-17-2011

Hi @avmohan,

 

There is no file to configure. You open your BD, and reconfigure the zynq in the IP integrator.

At this stage, you can go to the PS DDR controller panel and select the memory preset instead of the custom one.

--Sebastien
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Visitor
Visitor
1,655 Views
Registered: ‎05-20-2019

 

 

Hi, I have a same issue in our board. Our FPGA is XCZU9CG with MT40A512M16LY-062Ex2 (32bit)

We follow PG201 December 5, 2018 page 38 use preset config (MT40A256M16GE 083E), and modified as below, but we got same error 0xFD080030: 80C000FF.  We don't know how to modify the correct config for our board. Anyone know how to do?

Thank you.

ddr4.jpg

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Moderator
Moderator
1,580 Views
Registered: ‎01-09-2019

@leon.liu 

Since you are debugging a different issue, would you be willing to create a new forum post with your information?  That will allow it to be more easily seen by the appropriate source of help.

Thanks,
Caleb
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Observer
Observer
670 Views
Registered: ‎05-26-2015

avmohan, lot of time left, but still. Did you solve your problem with memory cause i have the same issue on my custom board and maybe you 

Lot of time left, but still. Did you solve your problem with memory cause i have the same issue on my custom board and maybe you can give me some advise 

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Observer
Observer
517 Views
Registered: ‎03-17-2017

Hi all,

Now it's our turn, we are facing the exact same issue with MT40A256M16GE-075E. 

@tomikaji @leon.liu were you able to solve this issue, if yes could you please let us know the resolution/workaround? 

Thanks,

Kiran

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Observer
Observer
507 Views
Registered: ‎05-26-2015

Hi, our custom board has DDR4 reset pin left unconnected. and it was issue. toggle to ground fix the problem. not sure you have exactly the same problem.
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Visitor
Visitor
468 Views
Registered: ‎05-20-2019

Hi kiranhollag, my problem was solved. My design have wrong DDR clk polarity, and fixed by correct. For you reference. 

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Observer
Observer
445 Views
Registered: ‎03-17-2017

@tomikaji @leon.liu Thanks for the quick reply, we will further debug our issue

 

Regards,

Kiran