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arslanmalik93
Observer
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Registered: ‎05-14-2018

Zynq Z0720 PCAP Readback

Hi,

I am trying to perfrom PL readback of Zedboard using PCAP but i am unable to find details regarding PCAP. I do not know the sewuence that i have to pass to xdev transfer function and no such details are provided in ug470. Can you please tell where can i find details on PCAP

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andresb
Xilinx Employee
Xilinx Employee
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Registered: ‎06-21-2018

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arslanmalik93
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Registered: ‎05-14-2018

Yes i have read ug 585 in the readback section of pcap chapter 6 there is only a slight overview example which tells the steps to be perfomed during readback.

I have also seen the second post u have shared before that posts only deal with how to write bitstream in pl using ps

What i i  interested in reading back the pl bitstream using ps for verification amd comparison.

I was wondering if there was any pl readback example just as Xilinix provide pl write bitstream example in xdevcfg templates

 

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gochango
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Registered: ‎06-12-2019

Is there any update to this issue?
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andresb
Xilinx Employee
Xilinx Employee
1,658 Views
Registered: ‎06-21-2018

Hi,
I would give it a try on the Embedded Config Forum as well:
https://forums.xilinx.com/t5/Embedded-Boot-and-Configuration/bd-p/EmbBoot
Thanks,
Andres
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arslanmalik93
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Registered: ‎05-14-2018

I am attaching the code i am using to perform PCAP readback as per instruction in u470. The code is based on Xilinx reg readback example can you look and tell if i am doing anything wrong?

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gochango
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Registered: ‎06-12-2019

Is this reading the actual PL bitstream thats already programmed? Or is it just reading the data being stored for the PL?

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arslanmalik93
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Registered: ‎05-14-2018

I am trying to read pl bitstream that i have programmed before and then performing ps readback. During readback the pl is shutdown(i inow because my pl code, blinking led stops all leds  goes to floating) bitstream readback shows all zeros 

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ap_32076
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Registered: ‎05-31-2019

Are there any updates to this? I am currently having the same issue with the output reading all 0s

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XuanXuanL
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Registered: ‎07-19-2020

Hello, did you solve this problem? I refer to the official example, but the data read back are all 0. I am very confused and don’t know how to solve it.

Zhejiang University,China;
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arslanmalik93
Observer
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Registered: ‎05-14-2018

Dear Xuan,

Yes i did solve the problem by slowing down the PCAP read clock from default 100Mhz to 50 Mhz.

If the read back is printing all zeroes chances are that their is no logic place on the FAR of PL you are trying to read from. Try to  place some glue logic on a known FAR and then read back from that location.

 

I am also attaching my pcap reading code along with a dummy main program in which i am calling that pcap reading function.. The code is straight forward.. you only have to pass a 32-bit FAR from where you want to read. The code readback and prints the output on UART (byte level flip view)

I wish you best of luck.

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XuanXuanL
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Registered: ‎07-19-2020

Dear arslan:
Thank you very much for your reply. I read your code carefully and benefited a lot. I modified the PCAP clock in my program, but the data read back is still all 0;
I don't know if there is a problem with my readback process. I immediately executed the readback program after downloading the bitstream in the SDK.
Below is my code. Can you help me find out where the problem is? Reading back the problem has troubled me for a long time. I really need your help, thank you very much! !


bd.png 

/*
 * axi dma test
 
*/
#include "dma_intr.h"
#include "sys_intr.h"

//!
#include <stdio.h>
#include "xdevcfg.h"
#include "xparameters.h"
//#include "platform.h"





#define DCFG_DEVICE_ID		XPAR_XDCFG_0_DEVICE_ID

/*
 * SLCR registers
 */
#define SLCR_LOCK	0xF8000004 /**< SLCR Write Protection Lock */
#define SLCR_UNLOCK	0xF8000008 /**< SLCR Write Protection Unlock */
#define SLCR_LVL_SHFTR_EN 0xF8000900 /**< SLCR Level Shifters Enable */
#define SLCR_PCAP_CLK_CTRL XPAR_PS7_SLCR_0_S_AXI_BASEADDR + 0x168 /**< SLCR
					* PCAP clock control register address
					*/

#define SLCR_PCAP_CLK_CTRL_EN_MASK 0x1
#define SLCR_LOCK_VAL	0x767B
#define SLCR_UNLOCK_VAL	0xDF0D

#define FRAMES          10008 //10008 //146
#define WORDS_PER_FRAME 101
#define rb_seq1_length 58

int XDcfgPolledExample(XDcfg * DcfgInstance, u16 DeviceId);
void PrintBitStream();

XDcfg DcfgInstance;		/* Device Configuration Interface Instance */
u32 readback_buffer[WORDS_PER_FRAME*FRAMES];
static u32 readback_seq1[rb_seq1_length] = {
		0xFFFFFFFF, //Dummy
		0x000000BB, //Bus width sync
		0x11220044, //Bus width detect
		0xFFFFFFFF, //Dummy
		0xAA995566, //Sync

		0x20000000, //NOP

		0x30008001, //Write to CMD
		0x0000000B, //SHUTDOWN command
		0x20000000, //NOP

		0x30008001, //Write to CMD
		0x00000007, //Reset CRC command
		0x20000000, //NOP

		0x20000000, //NOP
		0x20000000, //NOP
		0x20000000, //NOP
		0x20000000, //NOP
		0x20000000, //NOP

		0x30008001, //Write to CMD
		0x00000004, //RCFG command
		0x20000000, //NOP

		0x30002001, //Write to FAR
		0x0004e980, //partial Bitstream adress

		0x28006000, //Type 1 read FDRO
		0x48000000 | WORDS_PER_FRAME*FRAMES, //Type 2 read WORDS_PER_FRAME*FRAMES from FDRO

		0x20000000, 0x20000000, //2 NOPs

		//32 NOPs
		0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, //NOP
		0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, //NOP
		0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, //NOP
		0x20000000, 0x20000000 //NOP
};







static XScuGic Intc; //GIC
static  XAxiDma AxiDma;

volatile u32 success;


int Tries = NUMBER_OF_TRANSFERS;
int i;
int Index;
u8 *TxBufferPtr= (u8 *)TX_BUFFER_BASE;
u8 *RxBufferPtr=(u8 *)RX_BUFFER_BASE;
u8 Value;


int axi_dma_test()
{
	int Status;
	TxDone = 0;
	RxDone = 0;
	Error = 0;

	xil_printf("\r\n----DMA Test----\r\n");

	xil_printf("PKT_LEN=%d\r\n",MAX_PKT_LEN);


	//while(1)
	for(i = 0; i < Tries; i ++)
	{
		Value = TEST_START_VALUE + (i & 0xFF);
		for(Index = 0; Index < MAX_PKT_LEN; Index ++) {
				TxBufferPtr[Index] = Value;

				Value = (Value + 1) & 0xFF;
		}

		/* Flush the SrcBuffer before the DMA transfer, in case the Data Cache
		 * is enabled
		 */
		Xil_DCacheFlushRange((u32)TxBufferPtr, MAX_PKT_LEN);

		Status = XAxiDma_SimpleTransfer(&AxiDma,(u32) RxBufferPtr,
					MAX_PKT_LEN, XAXIDMA_DEVICE_TO_DMA);

		if (Status != XST_SUCCESS) {
			return XST_FAILURE;
		}

		Status = XAxiDma_SimpleTransfer(&AxiDma,(u32) TxBufferPtr,
					MAX_PKT_LEN, XAXIDMA_DMA_TO_DEVICE);

		if (Status != XST_SUCCESS) {
			return XST_FAILURE;
		}

		/*
		 * Wait TX done and RX done
		 */
		while (!TxDone || !RxDone) {
				/* NOP */
		}

		success++;
		TxDone = 0;
		RxDone = 0;

		if (Error) {
			xil_printf("Failed test transmit%s done, "
			"receive%s done\r\n", TxDone? "":" not",
							RxDone? "":" not");
			goto Done;
		}
		/*
		 * Test finished, check data
		 */
		Status = DMA_CheckData(MAX_PKT_LEN, (TEST_START_VALUE + (i & 0xFF)));
		if (Status != XST_SUCCESS) {
			xil_printf("Data check failed\r\n");
			goto Done;
		}

	}
	xil_printf("AXI DMA interrupt example test passed\r\n");
	xil_printf("success=%d\r\n",success);
	/* Disable TX and RX Ring interrupts and return success */
	DMA_DisableIntrSystem(&Intc, TX_INTR_ID, RX_INTR_ID);
Done:
	xil_printf("--- Exiting Test --- \r\n");
	return XST_SUCCESS;

}

int init_intr_sys(void)
{
	DMA_Intr_Init(&AxiDma,0);//initial interrupt system
	Init_Intr_System(&Intc); // initial DMA interrupt system
	Setup_Intr_Exception(&Intc);
	DMA_Setup_Intr_System(&Intc,&AxiDma,TX_INTR_ID,RX_INTR_ID);//setup dma interrpt system
	DMA_Intr_Enable(&Intc,&AxiDma);
}


int main(void)
{

//	init_intr_sys();
//	axi_dma_test();




	int Status;

	/*
	 * Call the example , specify the device ID that is generated in
	 * xparameters.h.
	 */
	Status = XDcfgPolledExample(&DcfgInstance, DCFG_DEVICE_ID);
	if (Status != XST_SUCCESS) {
		xil_printf("Dcfg Polled Example Test Failed\r\n");
		return XST_FAILURE;
	}

	xil_printf("Successfully ran Dcfg Polled Example Test\r\n");
	return XST_SUCCESS;


}


int XDcfgPolledExample(XDcfg *DcfgInstPtr, u16 DeviceId)
{


	int Status;
	u32 IntrStsReg = 0;
	u32 StatusReg;

	XDcfg_Config *ConfigPtr;
	XDcfg_ResetHw(DcfgInstance.Config.BaseAddr);
	/*
	 * Initialize the Device Configuration Interface driver.
	 */
	ConfigPtr = XDcfg_LookupConfig(DeviceId);

	/*
	 * This is where the virtual address would be used, this example
	 * uses physical address.
	 */
	Status = XDcfg_CfgInitialize(DcfgInstPtr, ConfigPtr, ConfigPtr->BaseAddr);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}


	Status = XDcfg_SelfTest(DcfgInstPtr);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}


	/*
	 * Enable the pcap clock.
	 */
	Xil_Out32(0xF8000008, 0xDF0D);
	Xil_Out32(0xF8000168, 0x701);
	Xil_Out32(0xF8000004, 0x767B);

	/*
	 * Select PCAP interface for partial reconfiguration
	 */
	XDcfg_EnablePCAP(DcfgInstPtr);
	XDcfg_SetControlRegister(DcfgInstPtr, XDCFG_CTRL_PCAP_MODE_MASK);


	/*
	 * Clear the interrupt status bits
	 */
	XDcfg_IntrClear(DcfgInstPtr, (XDCFG_IXR_PCFG_DONE_MASK |
					XDCFG_IXR_D_P_DONE_MASK |
					XDCFG_IXR_DMA_DONE_MASK));

	/* Check if DMA command queue is full */
	StatusReg = XDcfg_ReadReg(DcfgInstPtr->Config.BaseAddr, XDCFG_STATUS_OFFSET);
	if ((StatusReg & XDCFG_STATUS_DMA_CMD_Q_F_MASK) == XDCFG_STATUS_DMA_CMD_Q_F_MASK) {
		return XST_FAILURE;
	}

	/*
	 * Readback bitstream
	 */
	XDcfg_Transfer(DcfgInstPtr, (u32 *)readback_seq1, rb_seq1_length,
			(u32 *)readback_buffer, WORDS_PER_FRAME*FRAMES, XDCFG_PCAP_READBACK);


	/* Poll IXR_DMA_DONE */
	IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr);
	while ((IntrStsReg & XDCFG_IXR_DMA_DONE_MASK) !=
			XDCFG_IXR_DMA_DONE_MASK) {
		IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr);
	}

	/* Poll IXR_D_P_DONE */
	while ((IntrStsReg & XDCFG_IXR_D_P_DONE_MASK) !=
			XDCFG_IXR_D_P_DONE_MASK) {
		IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr);
	}
	PrintBitStream();

	/*
		 TO-DO: Restart fabric.
	*/

	return XST_SUCCESS;
}

void PrintBitStream()
{
	xil_printf("Print Bitstream\r\n");
	int i;
	for(i=0; i< WORDS_PER_FRAME * FRAMES; i++)
	{
			xil_printf("%08x\r\n", readback_buffer[i]);

	}
	xil_printf("Finished printing bitstream!\r\n");
}

 

 

Zhejiang University,China;
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