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stefanardo
Visitor
Visitor
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Registered: ‎06-25-2021

Zynq system with no DDR

Hi all,

does anyone experienced successfully with this tech tip

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842377/Zynq-7000+AP+SoC+Boot+-+Booting+and+Running+Without+External+Memory+Tech+Tip

and Vivado + Vitis 2020.2?

 

Regards.

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8 Replies
abommera
Xilinx Employee
Xilinx Employee
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Registered: ‎10-12-2018

Hi @stefanardo ,

Yes, I have verified this tech tip in version 2019.1 but not with 2020.2.

Thanks & Regards
Anil B
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stefanardo
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Registered: ‎06-25-2021

I am having 2 problems:

1)linker script, please can you provide the one is working with Vitis 2019?

2)flsbl loader in a system where DDR was disabled in the board design in Vivado.

Can you help me?

Regards

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dbwolfe
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Registered: ‎07-23-2021

@abommera, I am having the same problem trying to adapt this tech tip for Vitis.  The SDK projects cannot be imported directly, and the linker scripts provided in the tech tip break the Vitis GUI and do not seem to work correctly. 

I believe that I modified the FSBL source correctly based on the change list in the tech tip, but the default linker scripts in Vitis seem to have many extra fields compared the scripts in the example.  I modified them to the best of my ability, but when I try to program flash I get the following error:

 

Retrieving Flash info...

Initialization done
Using default mini u-boot image file - C:/Xilinx/Vitis/2021.1/data\xicom\cfgmem\uboot\zynq_qspi_x4_single.bin
===== mrd->addr=0xF800025C, data=0x00000000 =====
BOOT_MODE REG = 0x00000000
Downloading FSBL...
===== mrd->addr=0xF8000110, data=0x00177EA0 =====
READ: ARM_PLL_CFG (0xF8000110) = 0x00177EA0
===== mrd->addr=0xF8000100, data=0x0001A008 =====
READ: ARM_PLL_CTRL (0xF8000100) = 0x0001A008
===== mrd->addr=0xF8000120, data=0x1F000400 =====
READ: ARM_CLK_CTRL (0xF8000120) = 0x1F000400
===== mrd->addr=0xF8000118, data=0x00177EA0 =====
READ: IO_PLL_CFG (0xF8000118) = 0x00177EA0
===== mrd->addr=0xF8000108, data=0x0001A008 =====
READ: IO_PLL_CTRL (0xF8000108) = 0x0001A008
Problem in Initializing Hardware
Flash programming initialization failed.

ERROR: Flash Operation Failed

 

Debugging the code doesn't seem to work either, debug never enters the code section after programming the FPGA, and trying to pause the code gives an MMU error.

 

This is the console output after starting debug:

 

initializing
0% 0MB 0.0MB/s ??:?? ETA
27% 1MB 2.0MB/s ??:?? ETA
50% 1MB 1.8MB/s ??:?? ETA
74% 2MB 1.8MB/s ??:?? ETA
95% 3MB 1.7MB/s ??:?? ETA
100% 3MB 1.8MB/s 00:02

Downloading Program -- C:/Users/dbwolfe/source/repos/1x512_Zynq/FPGA/src/embedded/Zynq_Firmware/Zynq_Firmware/Debug/Zynq_Firmware.elf
section, .ro: 0xfc700000 - 0xfc700338
section, .init: 0xfc70033c - 0xfc700347
section, .fini: 0xfc700348 - 0xfc700353
section, .eh_frame: 0xfc700354 - 0xfc700357
section, .rw: 0x00010000 - 0x0001001f
section, .fini_array: 0x00010020 - 0x00010023
section, .init_array: 0x00010024 - 0x00010027
section, .heap: 0x00010028 - 0x0001202f
section, .stack: 0x00012030 - 0x0001402f

0% 0MB 0.0MB/s ??:?? ETA
100% 0MB 0.1MB/s 00:00

Setting PC to Program Start Address 0x00000000
Successfully downloaded C:/Users/dbwolfe/source/repos/1x512_Zynq/FPGA/src/embedded/Zynq_Firmware/Zynq_Firmware/Debug/Zynq_Firmware.elf
Info: ARM Cortex-A9 MPCore #0 (target 2) Stopped at 0x106f54 (Suspended)
xsct% Info: ARM Cortex-A9 MPCore #0 (target 2) Running

 

Pausing debug makes the disassembler window pop up with the following error:

Memory read error at 0x10000C. MMU section translation fault

This repeats for what looks like every memory location until I disconnect the debugger.

@stefanardo, can you let me know if you get any resolution to this problem?

Thanks,

Devin

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abommera
Xilinx Employee
Xilinx Employee
328 Views
Registered: ‎10-12-2018

Hi @stefanardo ,

I think you can download provided files (Zynq7000AP_SoC_BootingWithoutExternalMemory_2019.1.zip) in wiki page which covers hardware and software project source files.

@dbwolfe  I would suggest to try with provide files in 2019.1 rather than 2021.1. Then you can upgrade them to 2021.1.

Thanks & Regards
Anil B
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dbwolfe
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Registered: ‎07-23-2021

Hi @abommera,

I was able to get the example to work in 2018.2 SDK - the application and FSBL_XIP project import without issue.

I did some more experimentation in Vitis.  Instead of trying to make all of the modifications in the example separately, I just copied all of the sources over.  I started a platform project in Vitis with my exported hardware, and then replaced all of the sources for the platform FSBL and FSBL bsp with the sources from the FSBL_XIP project in the example, except for xparameters and xplatform.  The build process is failing at the linker script, with these errors:

 

arm-none-eabi-gcc -o fsbl.elf sd.o nand.o image_mover.o md5.o fsbl_hooks.o main.o nor.o qspi.o rsa.o ps7_init.o pcap
.o fsbl_handoff.o -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -
Wl,-build-id=none -specs=Xilinx.spec -lrsa -Wl,--start-group,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lxilffs,-lxil,-lgc
c,-lc,--end-group -Wl,--start-group,-lrsa,-lxil,-lgcc,-lc,--end-group -Wl,--gc-sections -Lzynq_fsb
l_bsp/ps7_cortexa9_0/lib -L./ -Tlscript.ld

c:/xilinx/vitis/2021.1/gnu/aarch32/nt/gcc-arm-none-eabi/x86_64-oesdk-mingw32/usr/bin/arm-xilinx-eabi/../../libexec/arm-xilinx-eabi/gcc/arm-xilinx-eabi/10.2.0/real-ld.exe: address 0x8000 of fsbl.elf section `.mmu_tbl' is not within region `FLASH'
c:/xilinx/vitis/2021.1/gnu/aarch32/nt/gcc-arm-none-eabi/x86_64-oesdk-mingw32/usr/bin/arm-xilinx-eabi/../../libexec/arm-xilinx-eabi/gcc/arm-xilinx-eabi/10.2.0/real-ld.exe: fsbl.elf section `.init_array' will not fit in region `FLASH'
c:/xilinx/vitis/2021.1/gnu/aarch32/nt/gcc-arm-none-eabi/x86_64-oesdk-mingw32/usr/bin/arm-xilinx-eabi/../../libexec/arm-xilinx-eabi/gcc/arm-xilinx-eabi/10.2.0/real-ld.exe: address 0x8000 of fsbl.elf section `.mmu_tbl' is not within region `FLASH'
c:/xilinx/vitis/2021.1/gnu/aarch32/nt/gcc-arm-none-eabi/x86_64-oesdk-mingw32/usr/bin/arm-xilinx-eabi/../../libexec/arm-xilinx-eabi/gcc/arm-xilinx-eabi/10.2.0/real-ld.exe: section .mmu_tbl VMA [0000000000004000,0000000000007fff] overlaps section .heap VMA [0000000000002364,000000000000436f]
c:/xilinx/vitis/2021.1/gnu/aarch32/nt/gcc-arm-none-eabi/x86_64-oesdk-mingw32/usr/bin/arm-xilinx-eabi/../../libexec/arm-xilinx-eabi/gcc/arm-xilinx-eabi/10.2.0/real-ld.exe: section .stack VMA [0000000000004370,000000000001176f] overlaps section .mmu_tbl VMA [0000000000004000,0000000000007fff]
c:/xilinx/vitis/2021.1/gnu/aarch32/nt/gcc-arm-none-eabi/x86_64-oesdk-mingw32/usr/bin/arm-xilinx-eabi/../../libexec/arm-xilinx-eabi/gcc/arm-xilinx-eabi/10.2.0/real-ld.exe: section .init_array VMA [0000000000008000,0000000000008003] overlaps section .stack VMA [0000000000004370,000000000001176f]
c:/xilinx/vitis/2021.1/gnu/aarch32/nt/gcc-arm-none-eabi/x86_64-oesdk-mingw32/usr/bin/arm-xilinx-eabi/../../libexec/arm-xilinx-eabi/gcc/arm-xilinx-eabi/10.2.0/real-ld.exe: region `FLASH' overflowed by 66095368 bytes
c:/xilinx/vitis/2021.1/gnu/aarch32/nt/gcc-arm-none-eabi/x86_64-oesdk-mingw32/usr/bin/arm-xilinx-eabi/../../libexec/arm-xilinx-eabi/gcc/arm-xilinx-eabi/10.2.0/real-ld.exe: fsbl.elf: section `.data' can't be allocated in segment 0
LOAD: .mmu_tbl .init_array .fini_array .text .handoff .init .fini .rodata .data
collect2.exe: error: ld returned 1 exit status
make: *** [Makefile:27: fsbl.elf] Error 1

 

I'm using the linker script from the example without any modifications.  Do you have any idea what is going on?  These same files build fine in the SDK.

Regards,

Devin

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stefanardo
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Registered: ‎06-25-2021

Already tryed with version 2019.1 (SDK) I have compilation errors on the FSBL project. With 2021.1 and Vitis tried to check line by line avery priece of code, but always linker problems.

 

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stefanardo
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Registered: ‎06-25-2021

The Vitis version is 2020.2 not 2021.1. Sorry

 

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dbwolfe
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Registered: ‎07-23-2021

@stefanardo@abommera,

I spoke too soon when I said I had the app note working - I was able to load the pre-generated BOOT.BIN file, but when I built the sources myself I got no UART output from the app.  It turns out that there is some important info missing from the app note that will prevent it from working.  I found a post describing a couple issues with the app note.  If you open it in Chrome, you can right click and translate it.

https://forums.xilinx.com/t5/%E5%B5%8C%E5%85%A5%E5%BC%8F-%E5%B7%A5%E5%85%B7-%E8%BD%AF%E4%BB%B6%E5%BC%80%E5%8F%91/%E5%88%86%E4%BA%AB-%E5%8D%87%E7%BA%A7Zynq-7000-XIP-%E5%8F%82%E8%80%83%E8%AE%BE%E8%AE%A1%E5%88%B0Xilinx-SDK-2018-3/td-p/1060349

First, the linker script error that pops up in SDK is not fatal - the output products are still created (FSBL_XIP.elf file).  Second, you have to modify the Application.bif file to specify offsets for the FSBL, bit file and application, plus a xip_mode flag for the FSBL.  SDK will overwrite the modified .bif file on import, so if you generate your own BOOT.BIN without making these mods it won't work.

For SDK 2019.1, I verified that I was able to build the projects and flash from the generated source, and that the app would run correctly.

-Devin

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