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chrisjrh
Observer
Observer
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Registered: ‎06-05-2017

ZynqMP Ultrascale+ AXI can't select 224G with 40-bit address

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I am trying to use the full 224GB for the following AXI interfaces:

  • S_AXI_HPM0_FPD (HPM0)
  • S_AXI_HPM1_FPD (HPM1)

Setting the offset addresses in Vivado to 0x0010_0000_0000 for HPM0 and 0x0048_0000_0000 for HPM1, as detailed in UG1085, only allows me to select 64G and 32G respectively:

 

axi.png

 

Where am I going wrong?

Thanks

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chrisjrh
Observer
Observer
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Registered: ‎06-05-2017

Hi Stephen,

 

Thanks for your reply, after playing around with that command for a bit it did the trick!

 

For reference the command for HPM0 is:

 

assign_bd_address [get_bd_addr_segs {ps/Data/SEG_M_AXI_HPM0_FPD_Regs}] -dict {offset 0x1000000000 range 64G offset 0x2000000000 range 64G offset 0x3000000000 range 64G offset 0x4000000000 range 32G} -external

By software implications do you just mean if the Xilinx AXI driver will work with it? If I update the range of the AXI bus in my device tree accordingly will everything be okay?

 

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stephenm
Xilinx Employee
Xilinx Employee
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Registered: ‎09-12-2007

Hey Chris,

 

The issue here is that the 224GB range is not alligned on a 2^n boundary, only on a 64GB one. Thus it would need multiple address ranges that are 64GB, or less to represent that entire possible range.

 

The dropdown in the IPI will only show ranges that can be assigned by the user. There is an option availabel to the user if they are using external interfaces to use the TCL command; assign_bd_address. This will let the user to map an external segments (128 + 64 +32) multiple times to different address. However, im not sure of the software implications here.

 

address.PNG

 

 

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stephenm
Xilinx Employee
Xilinx Employee
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Registered: ‎09-12-2007

Have you any further questions here?

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chrisjrh
Observer
Observer
1,036 Views
Registered: ‎06-05-2017

Hi Stephen,

 

Thanks for your reply, after playing around with that command for a bit it did the trick!

 

For reference the command for HPM0 is:

 

assign_bd_address [get_bd_addr_segs {ps/Data/SEG_M_AXI_HPM0_FPD_Regs}] -dict {offset 0x1000000000 range 64G offset 0x2000000000 range 64G offset 0x3000000000 range 64G offset 0x4000000000 range 32G} -external

By software implications do you just mean if the Xilinx AXI driver will work with it? If I update the range of the AXI bus in my device tree accordingly will everything be okay?

 

View solution in original post

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stephenm
Xilinx Employee
Xilinx Employee
874 Views
Registered: ‎09-12-2007
Software, as it accessing over the boundary. Its something I've never tested.

The DTG should work fine as this just uses info in the HDF.
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