03-31-2017 02:23 PM
I was reading this and wanted to do something similar:
But, I think the spi clk only runs when data is present. Is there another clock to use to run exterior logic with that runs continuously that is the same rate as the spi clk available?
04-02-2017 09:05 AM
For external logic you may want to try using fabric clock from PS to PL.
04-02-2017 09:43 AM
04-02-2017 03:54 PM - edited 04-02-2017 03:55 PM
Under clock configurations, my SPI clk is 166 MHz. I know that's NOT the spi clock for peripherals since I've measured them on an o-scope. As a matter of fact, the data sheet says the EMIO and MIO SPI clocks are limited to 25 and 50 MHz respectively. Where else is the SPI clk rate set?
04-02-2017 04:54 PM
The SPI clock is derived from the controller clock with the divider in the config register.
ug585 Zynq's TRM in Appendix B
That's the BAUD_RATE_DIV bits (5:3) and it can only divide by 4, 8, 16, 32, 64,128 and 256.
You could use an external divider but it will most likely not be synchronized with the bus clock the SPI controller generates.
Also to consider is if the controller reset its internal divider before a transaction.