12-16-2012 06:50 PM
I'm using ISE 13.4 system suit and I want to implement an axi-stream fft core in my microblaze system.
I understand that the CIP Wizard cannot generate an peripheral that contains axi-lite and axi-stream both ,so I have to generate
an axi-lite peripheral and add 2 axi-stream bus. But I still have some problem:
1.both axi-stream master port and slaver port contain a input clock , how can I connect the axi-stream master and slave while both their clock are input?
2.fft core has a configuration interface, how can I translate the axi-lite signal to the fft configuration port?
thank you very much!
12-17-2012 06:53 AM
1. If you look at Xilinx pcores, most of them pull out the axi_aclk signals for every interface and the user needs to drive them appropriately. That is, the clock inputs are not part of the bus_if in the .mpd.
2. You will probably need a shim between axi lite and axi stream to drive the config port of the FFT.
12-18-2012 06:56 PM
thank you for your reply!
1. you mean I need make the clock of master and slaver axi-stream interface to be a port ,not included in bus , is that right ?
2. I'm sorry I don't understand what is a shim , could you please explain it in detial?