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ggillett
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Registered: ‎08-14-2018

axi dma reset behvior

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Hi,

I am testing some DMA designs and have run into some perplexing reset behavior. The relevant part of the BD is

axi_test.png

 

axis_counter counts to some value asserting last at that value, it asserts valid one clock after coming out of reset (peripheral_aresetn). The axi_dma reset is connected to interconnect_aresetn. 

The issue is that axi_dma seems to expect 4 data beats after coming out of reset,

reset_ready.png

 

What is the dma IP expecting? The axi_dma registers are not changed by any of my test code, ext_reset_in to the reset IP is controlled through GPIO.

RegisterMap {
  MM2S_DMACR = Register(RS=0, Reset=0, Keyhole=0, Cyclic_BD_Enable=0, 
      IOC_IrqEn=0, Dly_IrqEn=0, Err_IrqEn=0, IRQThreshold=0, IRQDelay=0),
  MM2S_DMASR = Register(Halted=0, Idle=0, SGIncld=0, DMAIntErr=0, 
    DMASlvErr=0, DMADecErr=0, SGIntErr=0, SGSlvErr=0, SGDecErr=0, IOC_Irq=0, 
    Dly_Irq=0, Err_Irq=0, IRQThresholdSts=0, IRQDelaySts=0),
MM2S_CURDESC = Register(Current_Descriptor_Pointer=0),
MM2S_CURDESC_MSB = Register(Current_Descriptor_Pointer=0),
MM2S_TAILDESC = Register(Tail_Descriptor_Pointer=0),
MM2S_TAILDESC_MSB = Register(Tail_Descriptor_Pointer=0),
MM2S_SA = Register(Source_Address=0),
MM2S_SA_MSB = Register(Source_Address=0),
MM2S_LENGTH = Register(Length=0),
SG_CTL = Register(SG_CACHE=0, SG_USER=0),
S2MM_DMACR = Register(RS=0, Reset=0, Keyhole=0, Cyclic_BD_Enable=0, IOC_IrqEn=0, 
Dly_IrqEn=0, Err_IrqEn=0, IRQThreshold=1, IRQDelay=0),
S2MM_DMASR = Register(Halted=1, Idle=0, SGIncld=0, DMAIntErr=0, DMASlvErr=0, 
DMADecErr=0, SGIntErr=0, SGSlvErr=0, SGDecErr=0, IOC_Irq=0, Dly_Irq=0, Err_Irq=0, 
  IRQThresholdSts=0, IRQDelaySts=0),
S2MM_CURDESC = Register(Current_Descriptor_Pointer=0),
S2MM_CURDESC_MSB = Register(Current_Descriptor_Pointer=0),
S2MM_TAILDESC = Register(Tail_Descriptor_Pointer=0),
S2MM_TAILDESC_MSB = Register(Tail_Descriptor_Pointer=0),
S2MM_DA = Register(Destination_Address=0),
S2MM_DA_MSB = Register(Destination_Address=0),
S2MM_LENGTH = Register(Length=0)
}

Any insight appreciated.

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tedbooth
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Registered: ‎03-28-2016

@ggillett 

I would suspect that it is the AXIS interface logic on the input of the AXI DMA.  The AXIS interface logic is essentially a FIFO with a small amount of buffering.  I've seen similar behavior on multiple IPs with AXIS inputs.

Ted Booth | Tech. Lead FPGA Design Engineer | DesignLinx Solutions
https://www.designlinxhs.com

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tedbooth
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Registered: ‎03-28-2016

@ggillett 

I would suspect that it is the AXIS interface logic on the input of the AXI DMA.  The AXIS interface logic is essentially a FIFO with a small amount of buffering.  I've seen similar behavior on multiple IPs with AXIS inputs.

Ted Booth | Tech. Lead FPGA Design Engineer | DesignLinx Solutions
https://www.designlinxhs.com

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ggillett
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Registered: ‎08-14-2018

Hi,

Thanks that makes sense, the FIFO FWFT, register slices or what ever other buffering is ready and fills with the 4 data beats. 

The issue is when I perform a transfer that buffered data is missing and the buffer starts at 4. I'll check that I am setting up things correctly through PYNQ. 

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tedbooth
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Registered: ‎03-28-2016

@ggillett 

It is my understanding that the AXI DMA does not like it when data arrives before it is configured and running.  You might want to add a small bit of logic to control the flow of data on that channel.  Have it default to disabled until the AXI DMA is running and then enable it.

Ted Booth | Tech. Lead FPGA Design Engineer | DesignLinx Solutions
https://www.designlinxhs.com
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ggillett
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Registered: ‎08-14-2018

Hmm thanks for the heads up, don't particularly like the sound of that though. 

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