cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
paul12345
Observer
Observer
261 Views
Registered: ‎07-14-2020

axi_fifo_mm_s AXI-FIFO duplicates words; requires wrong TX length to operate; sets TSE flag

I am using axi_fifo_mm_s in 32-bit mode (AXI4-LITE only). I have a FIFO before and after it to cross clock domains since the input / AXI / output clock domains are 3 distinct clock domains. I have an ILA on both the input and output path and finally have observed something which has several issues I will describe here.

TCL that instantiates the block in question

create_bd_cell -type ip -vlnv xilinx.com:ip:axi_fifo_mm_s:4.2 axi_fifo_debug
set_property -dict [list CONFIG.C_USE_TX_CTRL {0} \
CONFIG.C_HAS_AXIS_TDEST {true} \
CONFIG.C_HAS_AXIS_TUSER {false} \
CONFIG.C_DATA_INTERFACE_TYPE {0} \
CONFIG.C_S_AXI4_DATA_WIDTH {32} \
CONFIG.C_USE_TX_CUT_THROUGH {0} \
] [get_bd_cells axi_fifo_debug]

And trying to send a packet. After much trial and error I have discovered what seem to be 3 bugs in the design of this IP:

1) it requires 8*number_of_words written to the TLR register, even though it should only require 4*number_of_words since I'm in 32-bit mode

2) It duplicates every word on the output. In other words, if I send 1, 2, 3, 4, it sends 1, 1, 2, 2, 3, 3, 4, 4, with tlast asserted on the final/second "4".

3) It sets the TSE (transmit size error) interrupt flag, indicating the wrong TLR length was written. I know I have written 8x and not 4x, but unless I do that, nothing comes out.

 

import periphery
fifo = periphery.MMIO(physaddr=0x800B0000, size=65536)

def push_tx_packet(vals, dest):
    vacancy = fifo.read32(offset=TDFV) & 0x1ffff  # 17-bit vacancy
    if vacancy < len(vals):
        print("Insufficient vacancy {:d} for length {:d} packet".format(vacancy, len(vals)))
        return
    fifo.write32(offset=TDR, value=dest & 0xf)  # 4-bit destination
    for val in vals:
        fifo.write32(offset=TDFD, value=val)
    fifo.write32(offset=TLR, value=len(vals) *   # in bytes

 

paul12345_0-1611786770950.png

paul12345_1-1611786838092.png

 

 

0 Kudos
1 Reply
paul12345
Observer
Observer
252 Views
Registered: ‎07-14-2020

I think it may actually have something to do with 32b vs 64b AXI buses somewhere in the PS / AXI interconnect. When I use devmem instead of periphery I do not see these bugs. The following would write 1,2,3,4 to destination 0x3, and use the expected width of 0x10 = 16 bytes.

devmem 0x800B002C 32 0x3

devmem 0x800B0010 32 0x1

devmem 0x800B0010 32 0x2

devmem 0x800B0010 32 0x3

devmem 0x800B0010 32 0x4

devmem 0x800B0014 32 0x10

devmem 0x800B0000 32

0x0DD00000

This indicates the following flags are set:

['RFPF', 'TFPF', 'RRC', 'TRC', 'RC', 'TC']

 

0 Kudos