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Observer
Observer
774 Views
Registered: ‎10-09-2018

axi_vip could not set data beat. allocated size * is too small for beat n

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when I simulate zynq 7000 with zynq7000 VIP, use datamover IP, some cmmand length will error  ncsim: *F,WARSEV (/opt/Xilinx/Vivado/2017.2/data/ip/xilinx/axi_vip_v1_0/hdl/axi_vip_v1_0_vl_rfs.sv,4408):

axi_vip_v1_0_2_pkg::axi_transaction.set_data_beat
[AR_REACTIVE_0] (axi_vip_v1_0_2_pkg::axi_transaction.set_data_beat) 4319 ns : Could not set data beat. Allocated size 64 is too small for beat ( 8).

can anybody tell me what does it mean?

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Xilinx Employee
Xilinx Employee
704 Views
Registered: ‎10-04-2016

Hi @bondylep,

Two thoughts for what you might be running into:

1. Is your data mover attempting to read from the Zynq 7000 PS DDR? It looks like there is a problem with the ARSIZE field in the read request.

2. There were a lot of issues with the slave ports in the Zynq 7000 VIP that were fixed in the 2018.1 release. The specific error you are running into does seem valid, though. However, as you continue to develop your test bench it would be best to upgrade to 2018.1 or 2018.2.

Regards,

Deanna

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Xilinx Employee
Xilinx Employee
705 Views
Registered: ‎10-04-2016

Hi @bondylep,

Two thoughts for what you might be running into:

1. Is your data mover attempting to read from the Zynq 7000 PS DDR? It looks like there is a problem with the ARSIZE field in the read request.

2. There were a lot of issues with the slave ports in the Zynq 7000 VIP that were fixed in the 2018.1 release. The specific error you are running into does seem valid, though. However, as you continue to develop your test bench it would be best to upgrade to 2018.1 or 2018.2.

Regards,

Deanna

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Observer
Observer
676 Views
Registered: ‎10-09-2018

I updated the vivado to 2018.2 by your suggesetion. but i encounter new problem, the zynq 7000 VIP API pre_load_mem_from_file does not have function, it is ok in 2017.2. 

thank you for your help

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Observer
Observer
672 Views
Registered: ‎10-09-2018

 I have check the ZYNQ7000 source code,it is becasue the new VIP mode pre_load_mem_from_file task add to check the address scale, my address is out of scale.

I hope the user can see as more source code as possible, so i can debug it bymyself.

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Visitor
Visitor
660 Views
Registered: ‎11-01-2018

hi,

   I'm using zcv104 evaluation borad, and the i encountered the same issue. I reduce the axi4 read outstanding num to 2, and the issue is dispeared.

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