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duanxiaoshan
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Registered: ‎04-13-2014

chipscope error: Coregen did not generate file

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hi,every one

       i am trying to build a embeded system with Planahead, and my ISE version is 14.3.I have obtained the liscense of ISE.

But when i used Chipscope ,there is error as follow:

      " Coregen did not generate file"
     how can i solve this problem?
    thanks
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siktap
Scholar
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6,838 Views
Registered: ‎06-14-2012

Thanks for the update. I am glad that the license issue is resolved.

On this one, Can you check if this solution?

 

http://forums.xilinx.com/t5/Embedded-Development-Tools/EDK-13-4-AXI-Chipscope-Monitor/td-p/224779

View solution in original post

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htsvn
Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

Hi,

 

Is this a System Edition or a Webpack license to start with?

 

Can you make sure that the path of the project has a smaller name? C:/example

 

Check the forum post as mentioned below:-

 

http://www.zedboard.org/content/xps-error-coregen-did-not-generate-file

 

--Hem

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siktap
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Registered: ‎06-14-2012

Can you paste the entire log? That will help.

 

If you already have a license file, there is a known issue with ISE 14.4

In the WebPACK tool install, the CORE Generator tool is not properly loading the available device families for the IP catalog. This prevents a device family from being loaded and causes all IP in the catalog to be listed as unavailable for the current device (grayed out).

To work around this issue, perform one of the following:

  • Use a full install of the ISE tools. The full install is larger, but uses the same executables as the WebPACK tool install. Devices and feature access will be controlled by the license available.
  • Set Environment variable XIL_CG_LOAD_ALL_FAMILIES=true

This issue is resolved in ISE Design Suite 14.5.

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duanxiaoshan
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Registered: ‎04-13-2014

hi, thank you all, i have solved the problem ,but there are new errors about chipscope when i implemented it, how can i solved it?

 

  • [NgdBuild 604] logical block 'cameradisplay_i/chipscope_axi_monitor_1/chipscope_axi_monitor_1/U_ILA' with type 'chipscope_axi_monitor_1' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'chipscope_axi_monitor_1' is not supported in target 'zynq'.  
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siktap
Scholar
Scholar
6,839 Views
Registered: ‎06-14-2012

Thanks for the update. I am glad that the license issue is resolved.

On this one, Can you check if this solution?

 

http://forums.xilinx.com/t5/Embedded-Development-Tools/EDK-13-4-AXI-Chipscope-Monitor/td-p/224779

View solution in original post

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duanxiaoshan
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Registered: ‎04-13-2014

yeah, it is just the solution, thank you very much.

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siktap
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Scholar
5,237 Views
Registered: ‎06-14-2012

@ duanxiaoshan   Can you please mark the thread solved with the solution?

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