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usernet
Visitor
Visitor
2,474 Views
Registered: ‎09-18-2009

errors in place the design

I use the XUPv5 board, use MPMC to control the DDR2. and when I run"hardware->generate bitstream" in XPS , errors below appear:

 

 

 Place:713 - IOB component "fpga_0_DDR2_SDRAM_DDR2_DQ<13>" and IODELAY component "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/g en_dq[13].u_iob_dq/u_idelay_dq" must be placed adjacent to each other into the same I/O tile in order to route net "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/g en_dq[13].u_iob_dq/dq_in". The following issue has been detected: Some of the logic associated with this structure is locked. This should cause the rest of the logic to be locked.A problem was found at site IODELAY_X0Y56 where we must place IODELAY DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/ge n_dq[13].u_iob_dq/u_idelay_dq in order to satisfy the relative placement requirements of this logic. IODELAY DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/ge n_dqs[0].u_iob_dqs/u_iodelay_dq_ce appears to already be placed there which makes this design unplaceable.

 

 

Does somebody can give me some advice about this error? thanks for your answer!!

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prateek_bhatt
Scholar
Scholar
2,452 Views
Registered: ‎08-21-2008

Hello.

Are you following the MIG generated UCF or some UCF of your own for DDR. 

Best of luck.
--
Unlimited in my Limits.
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