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tamasgy89
Observer
Observer
10,576 Views
Registered: ‎03-27-2008

ethernet controller implemented in FPGA

Hi,

 

  I'm trying to implement an Ethernet MAC controller without using EDK, processor, cores... I would only like to transmit data from FPGA to my computer (receive is not necessary) and I'm using a program called Wireshark to capture data. My question is what if I insert  a wrong source address in the frame? Does it matter? I think that the packet won't be thrown away because of that, but my transmission doesen't work...  or how can I get the address of my board? I'm using V2Pro or Spartan3E.

 

Thanks in advance,

Tamas

 

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brouhaha
Explorer
Explorer
10,568 Views
Registered: ‎08-14-2007

FPGA boards usually don't come with an assigned MAC address.  You can assign one yourself, either out of an official address block you can purchase from the IEEE, or in the "locally administered" portion of the address space.

 

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tamasgy89
Observer
Observer
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Registered: ‎03-27-2008

Thanks.

When I connect the Ethernet cable from the Virtex-II Pro to my PC, nothing happens, the "link up" LED does not turn on and I cannot see any sign of connection. When I connected the Spartan board, the LEDs started to flash and i could also see "notifications" on the PC that a connection was established. Do I have to do some kind of enable with the Virtex board? 

 

Tamas

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tamasgy89
Observer
Observer
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Registered: ‎03-27-2008

  Is it possible that my PHY is configured so that it won't start autonegotiation or parallel detection after power-up, and that's why it cannot create a link? However my PC does not see any connection, I should be able to send frames and receive them on the PC, no? I don't have any experience with Ethernet (I have never seen it working), so any kind of help is welcome.. :) 
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modelsim62c
Visitor
Visitor
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Registered: ‎05-10-2008

I don't know why the Spartan-3 board would power-up the LAN PHY to a 'working' state -- which board is it?

 

On most of Xilinx's devkits (ML40x, ML50x, etc.), the main FPGA will power-up to an uninitialized state -- all I/O's are tristate (and hence,  the LAN PHY's inputs are floating.)  Most PHYs require locally supplied clock-signal(s).  On the ML50x, the Marvell gigabit-PHY needs up to two clocks (1 for gigabit, other for 10/100 mode.)

 

*YOU must configure the FPGA to get the proper clock-signals to the LAN PHY.* Then you have to configure the PHY for the proper operational-mode.

 

On other FPGA-boards, the designers already did a lot of work for you. The PCB might have a dedicated clock-oscillator which is already connected to the PHY, so the FPGA doesn't need to worry about driving the clock, it just needs to turn on the appropriate enable-lines.

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tamasgy89
Observer
Observer
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Registered: ‎03-27-2008

  Hi,

thanks for the advices.

It's Spartan XC3S500E. Now the Virtex-II Pro does the power-up too, I forgot about the acitve-low reset signal of the PHY (enet_reset_z). The Spartan doesen't have such a signal...

 

 Thanks,

 Tamas

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