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Visitor
Visitor
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Registered: ‎06-03-2019

exclusive access in microblaze

Does any know how to enable exclusive access options for microblaze AXI DP?? 

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-12-2018

Re: exclusive access in microblaze

Hi @dipslg ,

Exclusive access is enabled using the two parameters C_M_AXI_DP_EXCLUSIVE_ACCESS and C_M_AXI_DC_EXCLUSIVE_ACCESS for the peripheral and cache interconnect, respectively

AXI4: Used to allow exclusive access when C_M_AXI_DP_EXCLUSIVE_ACCESS is 1

Please refer ug984 (v2018.3), page no.259 for reference.

Thanks & Regards
Anil B
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Visitor
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Registered: ‎06-03-2019

Re: exclusive access in microblaze

@abommera 

Thanks for replying. I have gone through this before. But the thing is in the block diagram there is no option to enable exclusive access. If I see the properties of the signal M_AXI_DP of microblaze than only AXI4LITE is enabled and no way I can change the option. In the VHDL code generated by the processor, I can see the option C_M_AXI_DP_EXCLUSIVE_ACCESS. So the qustion is if I alter the vhdl code and make the value to 1,  I am afraid it will do any changes with that I think I need to change the protocol setting of the microblaze and make it AXI4 and not sure what other signals need to be changed. 

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