cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
houssem1992
Observer
Observer
5,926 Views
Registered: ‎06-28-2015

filter design in vivado

Hi all ,

 

I try to design a customized filter on Zedboard and i use for that  an AXI Stream Slave and a Master Slave .

 

this block receive the data with the AXI Slave and send the output Signal  with Master . can someone help me to create the block .( i musst do that without fir compiler of xilinx )

in the main module of my filter i write this vhdl-code : 

 

-- Add user logic here

          process(m_axis_aclk) 
          
          begin
        
          
           
         if (m_axis_aclk='1') and (m_axis_aclk'event)  
              then
                   
                           --Verzögerung von Inputsignale bei jedem clockTakt 
                           c<=b;
                           b<=a;
                           a<=s_axis_tdata;
                           y<=(k1*a + k2*c);  -- Ausgangs Signal 
                           m_axis_tdata<=y(31 downto 0 ); -- Ausgangs auf die 32 Bits begrenzen 
          
                          end if ;  
          end process;  

-- User logic ends

for tvalid and tready inputs of dma and filter i connect them to a constant block (i  set them to 1 ) in the vivado my design .

 

my problem is that the transfer of data with SDK can not begin and i think it is a problem of the designed block .

 

please i need help to write the vhdl or verilog code .

 

Houssem

 

 

 

0 Kudos
1 Reply
morgan198510
Voyager
Voyager
5,915 Views
Registered: ‎04-21-2014


@houssem1992 wrote:

can someone help me to create the block  

 

 


Is this homework?

 

Anyway, research the axi protocol.  You may not get data every clock, and you may not want to send a new output every clock.

 

You will want to take new data when you're ready (you drive ready active) and the upstream indicates that the data is valid.

 

You will want to send new data when you can, and the downstream device indicates it's ready.

 

Start off by just making the downstream data equal to the upstream data (all pass filter). 

 

Make sure you get that working first. 

***Many of us who help you are just FPGA enthusiasts, and not Xilinx employees. If you receive help, and give kudos (star), you're likely to continue receiving help in the future. If you get a solution, please mark it as a solution.***