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ali_flt
Adventurer
Adventurer
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Registered: ‎08-10-2020

fix for AXI transaction hanging PS because of no initial reset

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Hi,
As I've experienced, if one has AXI-MM interfaces in any of their IP cores in the design, they have to reset that IP core after loading bitstream once before accessing the registers of that interface, otherwise the application (whether bare-metal or on OS) will hang the PS.
Now here is my use case:
I am running bare-metal applications inside Xen as guests and also doing dynamic function exchange for the specific region of PL dedicated for that guest. 
So the guest has a reconfigurable module, from which a partial bitstream is generated and loaded to their specific region. After that I assert a reset signal to that reconfigurable partition hoping this reset signal is connected to all IP cores inside the guest's design. Then the guest bare-metal application is executed inside Xen and inside that bare-metal application, the guest has accessed the AXI registers dedicated to him by Xen. 


Here is the issue: If I don't know what is inside the guest's reconfigurable module, I wouldn't know if they have connected my reset signal to all of their IP cores and if they haven't done that, the moment they access a register, the whole PS hangs. (not just the part dedicated to that guest)

First I would like to know why the whole PS freezes and not just that guest bare-metal application. Naturally I would think that if the CPU cores dedicated to a guest crash for any reason, other domains (Dom-0 and other guests) will not be affected by that guest. But here we see that that's not the case. 

Second I would like to know if anyone has a solution for the issue I just described.
Hope I explained the situation well.


Thanks and regards,
Ali

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ali_flt
Adventurer
Adventurer
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Registered: ‎08-10-2020

Hi @dgisselq ,
Thank you for your answer.
Yes, after posting this thread, I actually searched a little bit further myself and came across the AXI Firewall Protocol IP core which solved my issue.
As you mentioned the issue is exactly that a master is issuing transactions but no response is coming back which this Firewall can prevent by blocking transactions if they take more time than they should.

Regards,
Ali

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dgisselq
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Registered: ‎05-21-2015

@ali_flt ,

I'm not sure I follow completely ... you are using partial reconfiguration, and one or more AXI components are in the configuration region?  Are these AXI components slaves or masters?

As for what might lock up the entire design, well ... AXI is known for locking up an entire design if requests are made that don't get answers.  A request made of a component that is currently unconfigured, or that gets reconfigured mid request, would be likely to lock up an entire design.

One solution to this problem is to use an AXI firewall of some type.  I know my own example firewalls will allow AXI transactions through, while guaranteeing that responses are provided for all AXI transactions.  Failure to provide a valid response will then reset the downstream slave.  That said, I've only ever built a firewall to support an AXI slave.  I haven't (yet) built one to support an AXI master, hence my question above: Are your AXI components, within the partial reconfiguration region, slaves or masters?

Xilinx also offers an AXI firewall within their IP catalog.  I'm not sure if it can recover from a downstream failure, or if it will just leave the downstream bus offline following.

Dan

ali_flt
Adventurer
Adventurer
368 Views
Registered: ‎08-10-2020

Hi @dgisselq ,
Thank you for your answer.
Yes, after posting this thread, I actually searched a little bit further myself and came across the AXI Firewall Protocol IP core which solved my issue.
As you mentioned the issue is exactly that a master is issuing transactions but no response is coming back which this Firewall can prevent by blocking transactions if they take more time than they should.

Regards,
Ali

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