In a board including Zynq 7020 SoC, tx pin of a 422 transciever is both connected to PS MIO and FPGA pins. So both PL and PS are capable of driving it.
There was no problem because up to now only PS drived this transciever and PL pin is removed from top PL module. Now the requirement is that this TX pin will be driven by PS until bitstream is loaded (in the boot loader stage). After bitstream is loaded PL will drive the pin and PS never drives. Because PS UART is enabled in configuration, I assume it will drive this pin to logic '1' even I dont transmit any data from PS.
I read TRM of Zynq, I can disable transmitter operation of PS UART, but It did not clear to me if after disabling transmitter operation of PS UART the TX pin of PS UART will be open collector or pullup?
Does anyone know the answer or show me the document I can find information about PS UART tx pin behaviour after disabling the transmitter operation, or even disabling the UART peripheral completely?
I think even PS UART drives logic '1' to this pin, PL still can pull down it. So in practice I dont assume a problem occurs in baud rates below 2 mbps. Any comment on this also be very helpful.