we use Gigabit PHY (RTL8211) map at XCZU2EG 's gem3. As the interface of RGMII . PHY can set a 2ns skew between TXD/TXCTL and TXC with config pin pull up. it can also set 2ns skew between RXD/RXCTL and RXC with config pin pull up.
1. TXC/TXD come into PHY from MPSOC ,do we need to set a 2ns skew between TXC and TXD in PHY ?
2.RXC/RXD come into MPSOC from PHY, do we need to set a 2ns skew between RXC and RXD in PHY ?
@Zebulon : It depends on the RGMII interface of the MPSOC you're using...
If you're using the MIO-based RGMII, it does not have the ability to insert clock skew. (See Table 44 of DS925.) So you must skew both of the clocks at the PHY*.
If you're using an EMIO-based GMII and a GMII-to-RGMII IP core in the PL, the IP has the ability to insert skew in either clock, or not. In this case, you must decide which ONE device will insert skew in each the clock. I'd recommend using the PHY to insert skew in both clocks.
Hope this helps,
* You can always skew the clock using extra trace on TXC & RXC on your PCB. For the sake of this answer, I'll assume you only want to use skew-insertion at the PHY,or at the MPSOC.