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Registered: ‎05-08-2013

no signals from Ethernet to the PL?

Hello everybody,

    on our custom board, I have my ethernet going through the EMIO to the PHY. We are trying to probe the GMII_TXD,GMII_RXD and the clock pins using the chipscope. And, we see signals only on the TXclock and the RXclock and nothing on the data pins..


    As we are using linux, our device tree is just only populated with the very basic nodes.. Do we need more nodes in here for the FPGA, slcr, dev_cfg, etc..?


    Also, could this be anything to do with the base address of the slcr, dev_cfg if its wrong? are these files generated with the bsp from the XPS configuration?


Best regards,

Thanks in advance..

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Xilinx Employee
Xilinx Employee
Registered: ‎02-01-2008

In the XPS configuration, you select EMIO for ethernet. Then, when you export the design to SDK, a ps7_init.c and ps7_init.h file will be created by XPS and written into the SDK export directory. From this point, you would create a FSBL in SDK that will include the ps7_init files. One of the first things that FSBL will do is execute the ps7_init function which will program the registers to match what you configured in the XPS zynq tab.


So, make sure after you've set EMIO, that you export to SDK, and verify that the ps7_init.c .h files in the SDK export dir match the ps7_init files that appear in the SDK FSBL project src dir.


Then, you will use the boot utility to pull the FSBL with ps7_init settings, bit file (optional) and uboot elf files into BOOT.BIN.

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