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Explorer
Explorer
11,492 Views
Registered: ‎01-09-2009

problem in connecting microblaze to a custom IP

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Hi,

I have connected the microblaze to a custom IP (HDL block) using PLB. I used this tutorial to do so.

http://www.fpgadeveloper.com/2008/10/integrating-vhdl-design-into-peripheral.html

I just tried to change the tutorial a bit but I faced some problems. My HDL block is simply an adder that gets two 16-bit inputs and produces a 32-bit result (I know that is at most 17 bits :) ). The processor generates inputs to the adder and then it reads the result of adde asr shown below:

 

 

#include "xparameters.h"

#include "stdio.h"

#include "xbasic_types.h"
#include "xgpio.h"
#include "gpio_header.h"
#include "char_counter.h"
#include "xstatus.h"

#include <xio.h>
#include <stdlib.h>
#include "xuartns550_l.h"


Xuint32 *baseaddr_p = (Xuint32 *)XPAR_CHAR_COUNTER_0_BASEADDR;

int main (void) {

Xuint32 temp;
Xuint32 baseaddr;
char ch;

// Clear the screen
xil_printf("%c[2J",27);

print("-- Hello --\r\n");

// Check that the peripheral exists
XASSERT_NONVOID(baseaddr_p != XNULL);
baseaddr = (Xuint32) baseaddr_p;

xil_printf("CHAR COUNTER Test\n\r");

// Reset read and write packet FIFOs to initial state
CHAR_COUNTER_mResetWriteFIFO(baseaddr);
CHAR_COUNTER_mResetReadFIFO(baseaddr);

 

 // feeding the adder

temp = 33554430;
xil_printf("Wrote: 0x%08x \n\r", temp);
CHAR_COUNTER_mWriteToFIFO(baseaddr,0, temp);

temp = 33454430;
xil_printf("Wrote: 0x%08x \n\r", temp);
CHAR_COUNTER_mWriteToFIFO(baseaddr,0, temp);

temp = 36554430;
xil_printf("Wrote: 0x%08x \n\r", temp);
CHAR_COUNTER_mWriteToFIFO(baseaddr,0, temp);

// pop data out from read packet FIFO
temp = CHAR_COUNTER_mReadFromFIFO(baseaddr,0);
xil_printf("Read: 0x%08x \n\r", temp);
temp = CHAR_COUNTER_mReadFromFIFO(baseaddr,0);
xil_printf("Read: 0x%08x \n\r", temp);
temp = CHAR_COUNTER_mReadFromFIFO(baseaddr,0);
xil_printf("Read: 0x%08x \n\r", temp);

// Reset the read and write FIFOs
CHAR_COUNTER_mResetWriteFIFO(baseaddr);
CHAR_COUNTER_mResetReadFIFO(baseaddr);

xil_printf("End of test\n\n\r");

while(1){ }


return 0;
}

 

 As the code shows, I write three inputs and I expext three resuts, but all I got is zero ??

 

 

-- Hello --
CHAR COUNTER Test
Enter a character
Wrote: 0x01FFFFFE
Wrote: 0x01FE795E
Wrote: 0x022DC6BE
Read: 0x00000000
Read: 0x00000000
Read: 0x00000000
End of test

 

 here is my verilog code

 

module char_count (clk, test_a , test_b , test_p );

input clk ;
input [15:0] test_a;
input [15:0] test_b;
output reg [31:0] test_p;


always @(posedge clk)
begin
test_p <= test_a + test_b + 5;
end

endmodule

 

and here is the way that I connected the adder to PLB in the "user_logic.v"

 

 

....
// --USER logic implementation added here
char_count char_counter_0
(.clk(Bus2IP_Clk) , .test_a( WFIFO2IP_Data[0:15] ) , .test_b ( WFIFO2IP_Data[16:31] ) , .test_p(IP2RFIFO_Data[0:31]) );
....

 

 I would be grateful if someone can help to resolve this problem. I spent many hours to find the problem, but I couldn't.

 

 

 

 

 

 

 

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1 Solution

Accepted Solutions
Highlighted
13,502 Views
Registered: ‎02-07-2008

It looks like your "user_logic.v" file does not contain the FIFO loop-back example code. The tutorial uses that example code and inserts the multiplier in between the read and write FIFOs. Without the code for the loop-back, you wont have anything in the read FIFO, even after adding the multiplier.

 

Did you generate the peripheral using the Peripheral Wizard? You need to use the Peripheral Wizard and make sure that it generates the example code for the FIFOs.

View solution in original post

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9 Replies
Highlighted
11,464 Views
Registered: ‎02-07-2008
Post your entire "user_logic.v" file or send it to me and I'll have a look.
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Highlighted
Explorer
Explorer
11,471 Views
Registered: ‎01-09-2009

Jeffrey, please find the attachment.

 

Thank you for your help.

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Highlighted
Historian
Historian
11,447 Views
Registered: ‎02-25-2008

Well, you drive IP2Bus_Data with zero, so what made you think you'd get another result?

 

-a

----------------------------Yes, I do this for a living.
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Highlighted
Explorer
Explorer
11,442 Views
Registered: ‎01-09-2009

Thanks bassman59,

 

As far as I know, since I am using Read FIFO and write FIFO, I dont need to connect IP2Bus_Data to my IP. I think I just need to drive WFIFO2IP_Data.  Actually, I followed the tutorial in the link below to implement my costum IP.

http://www.fpgadeveloper.com/2008/10/integrating-vhdl-design-into-peripheral.html

it seems like they have also drive IP2Bus_Data with zero. I have attached their file as well. So, I think this signal doesn't any problem (may be I got you wrong)

They are interfacing uB to a multiplier using VHDL, but I am interfacing uB to an adder using Verilog. 

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Highlighted
13,503 Views
Registered: ‎02-07-2008

It looks like your "user_logic.v" file does not contain the FIFO loop-back example code. The tutorial uses that example code and inserts the multiplier in between the read and write FIFOs. Without the code for the loop-back, you wont have anything in the read FIFO, even after adding the multiplier.

 

Did you generate the peripheral using the Peripheral Wizard? You need to use the Peripheral Wizard and make sure that it generates the example code for the FIFOs.

View solution in original post

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Highlighted
Explorer
Explorer
11,388 Views
Registered: ‎01-09-2009

Jeffrey,

 

I again generated the user_logic.v using the Peripheral Wizard. Again, it did not contain the FIFO loop-back example. and Again, it didn't work. I then replaced the "user_logic.v" with a "user_logic.vhd" file that has the FIFO loop-back example. I then edited the VHDL code based on my custom IP. I also edited the PAO file to compile the VHDL user_logic file instead of verilog one. and it WORKS! 

So the conculsion that I made is that verilog files that  Peripheral Wizard generates are not reliable at all. Go with VHDL!

 

Thank you Jeffrey for your comments. It was helpful.

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Visitor
Visitor
7,960 Views
Registered: ‎02-16-2010

Hi,

 

I have followed most of the tutorials on the website you provided and I encountered the same problem when I was trying to rewrite the user_logic.vhd file into .v file. I thought I did it correct but on the hyper terminal I got outputs 0 all the way. I think user_logic should be working with both .vhd and .v files, but if you want to write your user_logic in verilog then EDK won't present you the exmaple code which will be generated in VHDL file. That's why I am studying VHDL instead of verilog now.

 

Is there anyone who has successfully rewritten user_logic.vhd file into .v file? Am I missing something important?

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Highlighted
Observer
Observer
7,311 Views
Registered: ‎09-20-2010

In the C file there is

 

#include "char_counter.h"

 

 

Char_counter.h is a library for custom peripheral ?

I made a project cery similar to that and  it doesnt work because  i dont have a file like that to my custom peripheral.

In XPS i press button gemerate libraries and driver and still there are no my_peripheral.h

Where can i get it ?

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Observer
Observer
7,305 Views
Registered: ‎09-20-2010

I founf that file ! Myperipheral.h

 

Now i write that in code (of course with #include myperipheral.h)

 

Myperipheral_mResetReadFIFO(baseaddr);

 

 And have error

 

undefined reference to `Myperipheral_mResetReadFIFO'

But there is such a function in Myperipheral.h    !!!!!

 

#define Myperipheral_mResetReadFIFO(BaseAddress) \
 	XIo_Out32((BaseAddress)+(MAIN_VHDL_MY_RDFIFO_RST_OFFSET), RDFIFO_RESET)

 Why C program dont see driver myperipheral.h ?

 

 

 

 

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