should the fifo be added to the axi interconnect ip ,when the salve and master is working in differernt domain ?

[microchip_zhang]

I have noticed that the "AXI Clock Converter" is used to transfer data from one clock domian to another clock domain, and the fifo is not used to do that, in general ,the fifo will be used to transfer data from one clock domian to another clock domain .  

do the "AXI Clock Converter"  just use two register to implement the Converting between the two clock domain, if so ,it seem to be not dependable ?

[adem369 · Accepted solution]

I think axi clock converter has the same logic with the async fifo inside it. Therefore, you can depend on it without adding fifo.