I build a ultra96v2 board just like below site. but in any case, I meet the error when doing "generate BitStream"
"design_1_zynq_ultra_ps_e_0_0_synth_1 failed"
tcl console and message have no error, and validate design is OK. However, why does this error cause, resulting in bitStream not completed?
https://highlevel-synthesis.com/how-to-create-ultra96v2-linux-based-platform-in-xilinx-vitis-2019-2/
https://qiita.com/basaro_k/items/6841c99c39ff12851847
