cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
chess2006
Visitor
Visitor
836 Views
Registered: ‎05-18-2018

why my xc7z020 A9 read ps ddr memory as all zero?

hello!

I have design/fab a xc7z020 board with external ps side 16bit ddr3 memory.

but when I perform ddr read from a9 processor jtag interface,

the memory allways return zero data, for all of the ddr address space.

I have check the following item:

1, power of vccint, vccaux, vccddr, ddrvref, vrefca, vrefdq is ok

2,the length of A0~A13, BA0~BA3, we, ras, cas,cs, cke, odt, reset, clkp, clkn have equal delay(including package delay) 

3,the length of DQ0~7, DM0,DQS0_P, DQS0_N have equal delay(including package delay)

4,the length of DQ8~15, DM1,DQS1_P, DQS1_N have equal delay(including package delay)

5,the length of data group is shorter than ctrl group

6,using same vivado project, zc702 work fine(in 16 bit mode), but my board can't 

 

the attachment of book1.xlsx are signal lengths of ddr trace.

and I can't figure out what's wrong with my board, 

could anybody give me some suggestion?

 

Tags (3)
0 Kudos
1 Reply
debrajr
Moderator
Moderator
769 Views
Registered: ‎04-17-2011

Since you have your board ready, try to run the Zynq DRAM Memory Test application in SDK. You will find that as a Template when you create an Application project in SDK.

The test is interactive as you would see in UART and run all the options. Once done copy the complete content in a text document and post back. That would give some clue.
Regards,
Debraj
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
0 Kudos