05-20-2018 03:38 AM
I have design/fab a xc7z020 board with external ps side 16bit ddr3 memory.
but when I perform ddr read from a9 processor jtag interface,
the memory allways return zero data, for all of the ddr address space.
I have check the following item:
1, power of vccint, vccaux, vccddr, ddrvref, vrefca, vrefdq is ok
2,the length of A0~A13, BA0~BA3, we, ras, cas,cs, cke, odt, reset, clkp, clkn have equal delay(including package delay)
3,the length of DQ0~7, DM0,DQS0_P, DQS0_N have equal delay(including package delay)
4,the length of DQ8~15, DM1,DQS1_P, DQS1_N have equal delay(including package delay)
5,the length of data group is shorter than ctrl group
6,using same vivado project, zc702 work fine(in 16 bit mode), but my board can't
the attachment of book1.xlsx are signal lengths of ddr trace.
and I can't figure out what's wrong with my board,
could anybody give me some suggestion?
05-24-2018 12:02 AM