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Registered: ‎10-28-2013

xapp744 - Hardware in the loop HIL simulation for the Zynq 7000, problems with AXI communication over JTAG

Hi everyone,


I followed the steps in the app note xapp744 to do a HIL simulation with the Zynq 7000.

The simulator ISim flashes successfully the bit file to the board:


ISim console output:

ISim P.68d (signature 0x7708f090)

This is a Full version of ISim.

Time resolution is 100 fs

at 0 fs: Note: Downloading bitstream, please wait till status is READY.


at 0 fs: Note: Bitstream download is complete. READY for simulation.


Simulator is doing circuit initialization process.

Finished circuit initialization process.



I'm able to start the debugger in the Xilinx SDK. It stops at the main function.


when i start the simulation in ISim with run all and start the program in the SDK after that with the resume button I get after some seconds the error message dialog in the SDK with following message:

target request failed: bogus trace status reply from target: timeout.

At the same moment the Simulation in ISim stops and returns:

ERROR: In process wrapperAHIL_CLK_0

Failed to perform hardware co-simulation run operation.

Error locking JTAG programming cable.

INFO: Simulator is stopped.


If I start it vice versa, first resume on SDK and run all after it in the ISim, I get the printf message

 Configuring the timer as an up-counter ...

but after some time the ISim stops with the same error message and the SDK terminates with:

Ignoring packet error, continuing...
Error while handling inferior event:
Remote 'g' packet reply is of odd length: E01
Ignoring packet error, continuing...


If I debug stepwise in the SDK the program runs until the first WRITE_REG() call. So the problem is the AXI connection over the JTAG...


I'm using PlanAhead 14.6, the Platform Cable USB II and the SDK 14.6.


Does anyone have an idea for my problem? Do you know when vivado will be able to do a HIL Simulation? Would it be promising to install the new version 14.7 of ISE?





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Registered: ‎10-28-2013

Re: xapp744 - Hardware in the loop HIL simulation for the Zynq 7000, problems with AXI communication over JTAG

finally I managed to run the HIL simulation.

The problem was the version of ISE. With ISE 14.2 it's working perfectly.

But I wonder why it doesn't work with newer versions and when vivado will support the co-simulation. Especially for SoC designs with the Zynq it's essential to have the ability to simulate the whole system (Hardware and Software in parallel)!


How do you do system validation in Zynq designs?




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