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Visitor rcordeau
Visitor
745 Views
Registered: ‎06-01-2016

AXI Chip2Chip with Aurora 8b10b Compact 2-1 setting not sticking after validate

Hi,
I have been trying to use AXI Chip2Chip and Aurora 8b10b in designs on 2017.4 -> 2019.1 with a sample project on a 7015 chip. The Chip2Chip will default to Compact 1-1 and want to use 2 lanes of the Aurora. I only have 1 lane, and I set the Aurora up this way, but no matter what I do, when I set the Chip2Chip to Compact 2-1 (which uses 1 lane), Vivado reverts it back to Compact 1-1 (which uses 2 lanes). This doesn't happen in 2016.4.  What am I missing??

 

Thanks,

Rob

10 Replies
Visitor rcordeau
Visitor
714 Views
Registered: ‎06-01-2016

Re: AXI Chip2Chip with Aurora 8b10b Compact 2-1 setting not sticking after validate

Well now I seem to know what it is - AXI Chip2Chip V5.0 will not do 32 bit. There is some bug that is preventing it. This problem doesn't exist in v4.2 of the IP. 

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Moderator
Moderator
661 Views
Registered: ‎03-25-2019

Re: AXI Chip2Chip with Aurora 8b10b Compact 2-1 setting not sticking after validate

Hi @rcordeau,

Do you see the same behaviour with a fresh design? If so, please share a screenshot showing the Chip2Chip Bridge IP Re-customize window.


If not, could you share your design then?
If yes, in this case if your design do not has any custom IP, you can execute the command bellow on the Vivado Tcl Console:

write_bd_tcl <file_name.tcl>

and share the generated TCL file. (The generated TCL script, allows to re-create the project from scratch).
Otherwise, I could send you a link in private to be able to send me the whole project.

Best regards,
Abdallah
-------------------------------------------------------------------------------
Please don't forget to reply, kudo and accept as a solution
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Visitor mmuller
Visitor
622 Views
Registered: ‎05-14-2018

Re: AXI Chip2Chip with Aurora 8b10b Compact 2-1 setting not sticking after validate

I am seeing the same issue on 2018.3, with axi_chip2chip 5.0. As soon as I validate the design it switches back to Compact 1-1, which changes the number of lanes to 2; instead of 1.

 

Here is the relevant section of the tcl file:

 

  # Create instance: axi_chip2chip_0, and set properties
  set axi_chip2chip_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_chip2chip:5.0 axi_chip2chip_0 ]
  set_property -dict [ list \
   CONFIG.C_AURORA_WIDTH {1} \
   CONFIG.C_AXI_DATA_WIDTH {32} \
   CONFIG.C_AXI_STB_WIDTH {4} \
   CONFIG.C_ECC_ENABLE {false} \
   CONFIG.C_EN_AXI_LINK_HNDLR {true} \
   CONFIG.C_INTERFACE_MODE {1} \
   CONFIG.C_INTERFACE_TYPE {3} \
   CONFIG.C_NUM_OF_IO {20} \
 ] $axi_chip2chip_0

  # Create instance: axi_chip2chip_0_aurora8, and set properties
  set axi_chip2chip_0_aurora8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:aurora_8b10b:11.1 axi_chip2chip_0_aurora8 ]
  set_property -dict [ list \
   CONFIG.C_DRP_IF {false} \
   CONFIG.C_LANE_WIDTH {4} \
   CONFIG.C_LINE_RATE {6.25} \
   CONFIG.C_REFCLK_FREQUENCY {156.250} \
   CONFIG.C_USE_BYTESWAP {true} \
   CONFIG.C_USE_CRC {false} \
   CONFIG.Flow_Mode {None} \
   CONFIG.Interface_Mode {Framing} \
   CONFIG.SINGLEEND_GTREFCLK {true} \
   CONFIG.SINGLEEND_INITCLK {true} \
   CONFIG.SupportLevel {1} \
   CONFIG.TransceiverControl {true} \
 ] $axi_chip2chip_0_aurora8

 

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Observer michaelellis
Observer
561 Views
Registered: ‎03-27-2019

Re: AXI Chip2Chip with Aurora 8b10b Compact 2-1 setting not sticking after validate

@abouassi,

I am seeing the same problem with Vivdo 2019.1 using the AXI Chip2Chip Bridge 5.0.  I customize the IP and set the PHY Width to Compact 2-1 and say OK to exit the customize screen.  When I run Validate Design I get two critical warnings [BD 41-237] related to TDATA_NUM_BYTES mismatch, one for Tx and one for Rx.  If I then customize the IP I see that the PHY Width has reverted to Compact 1-1.  I also see odd messages in the TCL console when I exit the customize screen after changing the PHY Width.

See attached file for screenshots.

 

 

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Observer wpekrul_bnl
Observer
397 Views
Registered: ‎09-13-2017

Re: AXI Chip2Chip with Aurora 8b10b Compact 2-1 setting not sticking after validate

I see the same bug in 2018.2 with a zynq 045. Has anyone posted a fix? It happens with a zynq master but not an artix slave.

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Highlighted
Xilinx Employee
Xilinx Employee
371 Views
Registered: ‎03-30-2016

Re: AXI Chip2Chip with Aurora 8b10b Compact 2-1 setting not sticking after validate

Hello @rcordeau , @wpekrul_bnl , @michaelellis , @mmuller 

This is a known issue. This issue still exist in 2019.2. (Issue will not occurs with C2C Mode=Slave setting)
Unfortunately there is no work-around for this issue.

 

Confirmed in internal database that fix is scheduled for future Vivado release, but not until 2020.1.
Apologize for any inconnivience caused.

Regards
Leo

Observer michaelellis
Observer
343 Views
Registered: ‎03-27-2019

Re: AXI Chip2Chip with Aurora 8b10b Compact 2-1 setting not sticking after validate

@rcordeau@wpekrul_bnl@karnanl@mmuller,

 

I filed an SR with Xilinx support and eventually was given a patch that worked for me.  The patch was AR73018 for Vivado 2019.1 but I'm not sure if it will work with other versions.

 

Regards,

Michael

 

Observer wpekrul_bnl
Observer
315 Views
Registered: ‎09-13-2017

Re: AXI Chip2Chip with Aurora 8b10b Compact 2-1 setting not sticking after validate

Thank you for the pointer. I applied the patch to 2018.2 and it compiled. Now to the hardware.

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Observer wpekrul_bnl
Observer
213 Views
Registered: ‎09-13-2017

Re: AXI Chip2Chip with Aurora 8b10b Compact 2-1 setting not sticking after validate

With ar73018 applied my master and slave projects compile and I get communication from the master to a gpio block on the slave. When I connect an axi bram controller and a block memory configured as ram or rom to the c2c/aurora 8b10b slave I get bus errors at the master side. Any suggestions?

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Observer wpekrul_bnl
Observer
130 Views
Registered: ‎09-13-2017

Re: AXI Chip2Chip with Aurora 8b10b Compact 2-1 setting not sticking after validate

I am pretty sure that the the qplllock_out and qpllrefclklost_out pins are swapped on the c2c master IP block. I read them as continuously low and high respectively indicating errors while the interface is transfering data perfectly. On the c2c slave they are continuously high and low as expected.

BTW, the bus error problem from my previous post turned out to be pilot error.

 

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