UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Adventurer
Adventurer
3,794 Views
Registered: ‎09-19-2016

AXI DMA in SG : Interrupt generated before given number of BDs are processed?

Jump to solution

Hi people,

 

We have our custom module that sends data to Axi DMA which works in SG mode. Through software we set DMA to generate interrupt after N number of packets are transferred (we do that with Coalescing counter) from our module to DDR. So, number of BDs we want to transfer is N * BDS_PER_PKT = X. It happens that DMA generates interrupt but when we get number of processed BDs from hardware (with XAxiDma_BdRingFromHw function) that number is often X-1, or X-2, sometimes even X-3 or X-4. So, number of BDs processed and transferred by DMA is smaller than number we defined. Confusing thing is that DMA generates interrupt regardless of that, as though right number of BDs are processed. More confusing thing is that when we check what is written to memory sometimes everything is transferred as expected, but more often we miss that size ((X-1)*MAX_PKT_LEN, (X-2)*MAX_PKT_LEN, etc...) of data in memory.  

Where could be a problem, any hint?

 

Regards

0 Kudos
1 Solution

Accepted Solutions
Adventurer
Adventurer
7,068 Views
Registered: ‎09-19-2016

Re: AXI DMA in SG : Interrupt generated before given number of BDs are processed?

Jump to solution

Thanks for answer, but it seems that we solved the problem in the meantime. And the problem was, of course, our module, which had some kind of latency when generating signals tlast and tvalid. 

0 Kudos
2 Replies
Xilinx Employee
Xilinx Employee
3,719 Views
Registered: ‎08-01-2012

Re: AXI DMA in SG : Interrupt generated before given number of BDs are processed?

Jump to solution

Below forum thread are having related discussions with respect to your query. Please check whether they are useful for you

https://forums.xilinx.com/t5/Embedded-Development-Tools/Axi-DMA-in-SG-multi-channel-mode/td-p/558997

https://forums.xilinx.com/t5/Zynq-All-Programmable-SoC/how-to-get-peak-throughput-for-AXI-DMA/td-p/667827

________________________________________________

Please mark this post as an "Accept as solution" in case if it helped to resolve your query. So that it will help to other forum users to directly refer to the answer.

Give kudos to this post in case if you think the information is useful and reply oriented.

0 Kudos
Adventurer
Adventurer
7,069 Views
Registered: ‎09-19-2016

Re: AXI DMA in SG : Interrupt generated before given number of BDs are processed?

Jump to solution

Thanks for answer, but it seems that we solved the problem in the meantime. And the problem was, of course, our module, which had some kind of latency when generating signals tlast and tvalid. 

0 Kudos