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Visitor jstoezel
Visitor
612 Views
Registered: ‎06-25-2015

AXI HP slave to DDR dies, eventually

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Hi:

 

I have an AXI HP slave connected to an external AXI master interconnect. I use this interface to dump data from the PL to the PS on a Zynq system.

I have configured the AXI transfers as follows: S_AXI_WDATA_i <= bram_doutb;
AWSIZE <= "010"; -- 4 bytes per beat
AWLEN <= x"FF"; -- 256 burst length
AWBURST <= "01"; -- INCR
AWLOCK <= "00"; -- NORMAL access
AWCACHE <= "0000"; -- Device is non bufferable
AWID <= '0';
AWQOS <= "0000";

I can generate bursts (total of 4 per dump to DDR) and the data is properly stored in DDR. Everything seems to work perfectly until the 31st or 32nd burst group. On the very first transaction the HP slave does not respond to an address or data write (AWREADY and WREADY never set after a AWVALID or WVALID is set).

The device never seems to recover after this, and I need to reset the chip to get out of this situation.

I am not sure where to start to debug this, the issue is reproducible though, the issue manifests itself on the 31 or 32nd burst group. Is this related to the AWLOCK/AWCACHE/AWQOS settings?

 

Regards,
JS

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1 Solution

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Voyager
Voyager
531 Views
Registered: ‎02-01-2013

Re: AXI HP slave to DDR dies, eventually

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ISE--and EDK? Ewww... You should have led with that. I'd recommend moving to Vivado, if possible, especially for a Zynq design.

The 64-bit limitation on the data width of the HP AXI port is a chip thing, not a tool thing.

2019-01-20_10-04-45.jpg

The action to set the width of the interface is roughly the same in EDK:

2019-01-20_10-57-24.jpg

as it is in Vivado:

2019-01-20_10-10-35.jpg

If you had difficulty attaching a 32-bit connection to that port, it's probably because it was configured to be 64 bits, and you weren't accounting for connection re-mapping. See TRM, section 5.3.6.

My comment about looking at the connection between the Zynq and the AXI Interconnect probably seems strange in the EDK environment. In Vivado, the AXI Interconnect is a separate IP block. It's straightforward there to instrument the distinct AXI between the Interconnect and the Zynq, as well as the other AXI between your master and the Interconnect.

It's been so long since I've used ISE for an embedded Zynq system, I'm not sure how to guide you in debugging that. You're right: it might be easier for you to re-write your IP as an AXI-3 master.  I can't remember if the EDK interconnect does all the nifty re-arranging and auto-fixing that the Vivado interconnect does.

The GP AXI can support bursts, but it's meant to allow PL access to all PS resources.  The path through the PS to the DDR is less optimized from the GP AXI port:

2019-01-20_11-30-00.jpg

2019-01-20_11-19-15.jpg

-Joe G.

 

 

4 Replies
Voyager
Voyager
595 Views
Registered: ‎02-01-2013

Re: AXI HP slave to DDR dies, eventually

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The HP port of the Zynq is an AXI-3 interface. AXI-3 supports only 16-beat bursts. Since the interface is also only capable of moving 64 bits, it's more than coincidence that your AXI activity locks-up after 32, 32-bit transfers. I'd look at the configuration of the AXI Interconnect you're putting between your IP and the AXI port; one of its responsibilities is to break-up the (up to 256-beat) AXI-4 bursts into AXI-3 bursts.

How are the B-channel responses from the AXI Interconnect for the writes?  Are they all coming back OKAY? How about the responses from the Zynq to the AXI Interconnect?

-Joe G.

 

Visitor jstoezel
Visitor
552 Views
Registered: ‎06-25-2015

Re: AXI HP slave to DDR dies, eventually

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Hi Joe:

Thanks for your reply.


To address your comments/questions:
- I have the axi interconnect setup as an AXI4, I did not know the HP ports only support AXI3... I am issuing 256 beat bursts. It may be easier if I were to switch the interconnect to AXI3 and issue 16 beat bursts.
- There is an option to switch the HP to 32 or 64 bits (I am using ISE 14.7-not sure if this would be limited to 64 in other versions). I could not get the DDR dump to work properly until I switched o 64 bits.
- The B-channel responses from the AXI interconnect look ok: the interconnect is ack-ing (BVALID set) the writes at the end of each 256 beat burst and BRESP is set to OK.
- I don't have anything instrumenting the AXI between the ZYNQ and the AXI (debugging straight on the hardware).

I have this working with an AXI GP port, the interface never dies with ta GP (single beat writes). My understanding is that the GP does not support burst though, and I have observed that the GP is much slower than the HP (when the HP is used in burst mode).

JS

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Voyager
Voyager
532 Views
Registered: ‎02-01-2013

Re: AXI HP slave to DDR dies, eventually

Jump to solution

 

ISE--and EDK? Ewww... You should have led with that. I'd recommend moving to Vivado, if possible, especially for a Zynq design.

The 64-bit limitation on the data width of the HP AXI port is a chip thing, not a tool thing.

2019-01-20_10-04-45.jpg

The action to set the width of the interface is roughly the same in EDK:

2019-01-20_10-57-24.jpg

as it is in Vivado:

2019-01-20_10-10-35.jpg

If you had difficulty attaching a 32-bit connection to that port, it's probably because it was configured to be 64 bits, and you weren't accounting for connection re-mapping. See TRM, section 5.3.6.

My comment about looking at the connection between the Zynq and the AXI Interconnect probably seems strange in the EDK environment. In Vivado, the AXI Interconnect is a separate IP block. It's straightforward there to instrument the distinct AXI between the Interconnect and the Zynq, as well as the other AXI between your master and the Interconnect.

It's been so long since I've used ISE for an embedded Zynq system, I'm not sure how to guide you in debugging that. You're right: it might be easier for you to re-write your IP as an AXI-3 master.  I can't remember if the EDK interconnect does all the nifty re-arranging and auto-fixing that the Vivado interconnect does.

The GP AXI can support bursts, but it's meant to allow PL access to all PS resources.  The path through the PS to the DDR is less optimized from the GP AXI port:

2019-01-20_11-30-00.jpg

2019-01-20_11-19-15.jpg

-Joe G.

 

 

Visitor jstoezel
Visitor
494 Views
Registered: ‎06-25-2015

Re: AXI HP slave to DDR dies, eventually

Jump to solution

Hi Joe:

Thanks for the reply. At this time I am stuck with ISE for this legacy project (I do use Vivado on newer projects).

I switched the interconnect interface to AXI3, and limited the burst size to 16 beats bursts, and things are working ok.

I read somewhere that even though AXI3 is limited in the standard to 16 beat bursts, it is common practice for vendors to support 256 beat bursts on AXI3. I did try 256 beats and it did not work (slave stops acking after 16 beats). For now I will be using 16 beat bursts.

Thank you for the help, very much appreciated.

 

Regards,

JS

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