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Visitor ltv1729
Registered: ‎07-17-2019

AXI IIC core clock stretching

The AXI IIC core has problems talking to an I2C device that clock stretches.

I am running Linux on a Zedboard.  The Zedboard is the I2C master; another device is the I2C slave; these are the only two devices on the I2C bus.  If I use the I2C interface built into the PS, it works fine.  I have an FPGA .bit image in which an AXI IIC interface has been instantiated.  That PL interface also works fine, unless the slave device clock stretches.  If the slave device clock stretches, the AXI IIC core in my PL fails.  It appears that the AXI IIC core doesn't support talking to slave devices that clock stretch.

The FPGA .bit file was built with Vivado 2019.1.

I tried using the most up-to-date AXI IIC device driver source from github.  I also tried bypassing the Linux device driver completely by updating the IIC core registers in my own program, using the instructions in the file pg090-axi-iic.pdf under the heading "Pseudo code for dynamic IIC accesses."  Neither of those things does any good.  When I look at SDA and SCL on an oscilloscope, it looks like the data line is being pulled low while the Zynq is trying to sample it.

Any help anyone could give me would be appreciated.  Thank you.

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Registered: ‎07-31-2012

Re: AXI IIC core clock stretching

Hi @ltv1729 ,

Few points you may need to look into pull up resistors if it is sufficient or not.

May need to wait for few more cycle to see if SDA line is not low forever.



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