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Visitor ajowsey
Visitor
713 Views
Registered: ‎01-03-2019

AXI Quad SPI FIFOs with Multiple Discrete 8-bit Transfers

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Hey there,

I am using an axi_quad_spi module in standard legacy mode to communicate with a device that requires discrete 8 bit messages. I am also using a FIFO with this module because I found that I was experiencing 24us between each byte otherwise. I saw in the manual, bottom of page 72, that I should be able to limit my word to 8 bits without requiring anything like automatic slave select as long as my transaction width (C_NUM_TRANSFER_BIT) is set to 8.

Problem is that when I tried implementing the steps laid out on page 72 and 73 (using devmem or basic ioct), I see all my fifo bytes being truncated. Rather than have a break or chip select toggled between 8 bits.  Im not sure if I am expecting the wrong behavior or if my settings are just not correct.

Screenshot from 2019-01-03 15-10-53.png

 

 

 

 

 

Do you have any advice? 

Here is the script I wrote to test it:

 

#!/bin/sh

# 1. Basic Initialization
echo ""
echo "Read and clear interrupts"
devmem 0xA80D0020 				# to clear interrupts - 1
devmem 0xA80D0070 32 0xffffffff		        # clear SS - 1
devmem 0xA80D0060 32 0x1e6 			# inhibit transaction -1

# 2. Setup for multi-byte
# ~> Default is fine: devmem 0xA80D001C 32 0x00000000		# configure DGIER (Device Global Int En Reg) - 2
# ~> Default is fine: devmem 0xA80D0028 32 0x00000000		# configure IPIER (IP Int En Reg) - 2

# 3. and 4.
devmem 0xA80D0060 32 0x00000000		# write data to master SPICR 

# 5. Select the slave
devmem 0xA80D0070 32 0xfffffffe 	# set SS - 5

# 6. and 7. Send Transaction
devmem 0xA80D0068 8 0xDE			
devmem 0xA80D0068 8 0xAD			
devmem 0xA80D0068 8 0xBE		
devmem 0xA80D0068 8 0xEF			

echo ""
echo "Read out buffer occupancy: x + 1 = number of bytes"
devmem 0xA80D0074					# read out fifo - 6 and 7

echo ""
echo "Send buffer"
devmem 0xA80D0060 32 0x86  			        # write data to master SPICR - 8 

echo ""
echo "Read and clear interrupts"
devmem 0xA80D0020 					# to clear interrupts - 9 and 10

echo ""
echo "Read and clear interrupts"
devmem 0xA80D0064 					# Read SPISR reg - 11 and 12

 

And here is a breakdown of my TCL components script:

 

create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_spi_0
set_property -dict [list CONFIG.C_USE_STARTUP {0} \
                         CONFIG.C_NUM_SS_BITS {1} \
                         CONFIG.C_XIP_MODE {0} \
                         CONFIG.C_TYPE_OF_AXI4_INTERFACE {0} \
                         CONFIG.Master_mode {1} \
                         CONFIG.C_NUM_TRANSFER_BITS {8}\
                         CONFIG.FIFO_INCLUDED {1} \
                         CONFIG.C_USE_STARTUP_INT {0} \
                         CONFIG.C_SCK_RATIO {16} \
                         CONFIG.C_FIFO_DEPTH {256}] [get_bd_cells axi_spi_0]

 

 

 

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1 Solution

Accepted Solutions
Scholar jg_bds
Scholar
503 Views
Registered: ‎02-01-2013

Re: AXI Quad SPI FIFOs with Multiple Discrete 8-bit Transfers

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"Discrete 8-bit Transfers" refers to the movement of a single byte in a transaction. (See my definition of a transaction above.) Your interface requires such a transfer, but some don't.  SPI interfaces with some EEPROMs, for example, allow long transfers of bytes in a single transaction--effectively 'bursting' data across the interface. PG153, in its examples, is distinguishing a scenario where a single byte is being transferred in multiple transactions, as opposed to--for example--a different scenario where multiple bytes are transmitted during a single transaction from the SPI FIFO.

-Joe G.

 

 

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Scholar jg_bds
Scholar
539 Views
Registered: ‎02-01-2013

Re: AXI Quad SPI FIFOs with Multiple Discrete 8-bit Transfers

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"truncated"? How are the bytes truncated?  I count 32 clocks in the transfer waveforms you show, and the data appears to spell-out "DE AD BE EF". All 32 bits are going out. I cannot see truncation.

-Joe G.

 

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Scholar jg_bds
Scholar
534 Views
Registered: ‎02-01-2013

Re: AXI Quad SPI FIFOs with Multiple Discrete 8-bit Transfers

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I get it now...

You're getting the behavior that you're asking for; it's just not the behavior you want.

By using the FIFO to 'speed up' your transfers, you're instead causing all of your bytes to be sent out during the same transaction. 

Chip select assert... transfer data... chip select de-assert. <- That's a single transaction.

It seems like you rather want only one byte to be transferred during every transaction.  In that case, either put only one byte in the FIFO, or don't use a FIFO. 

You probably also want to enable automatic chip-select. That way, the toggling of chip select will occur at the beginning and the end of each transaction--you won't need to do it explicitly.

If you want the transactions to occur at a faster rate, compile some code.  Running a script means each step in the script needs to pass through an interpreter before invoking a function, in order for you to get what you want done. All that overhead accumulates into delays. Compiled code will run faster.

-Joe G.

 

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Visitor ajowsey
Visitor
512 Views
Registered: ‎01-03-2019

Re: AXI Quad SPI FIFOs with Multiple Discrete 8-bit Transfers

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@Joe G

I think you may be correct but I am confused what the manual is trying to describe with "Discrete 8-bit Transfers" if it has a Fifo. Im hoping to confirm before I jump to an alternate solution.

I have compiled code that uses ioctl that eventually has the callstack of something like application.o->spi.ko->spidev.ko->spi-xilinx.ko->axi_quad_spi but the latency is really caused by stitching between userspace and kernel space. So if what I want isn't available, I'll probably need to write a kernel module that feeds a buffer to spidev to avoid bad latency.

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Visitor ajowsey
Visitor
511 Views
Registered: ‎01-03-2019

Re: AXI Quad SPI FIFOs with Multiple Discrete 8-bit Transfers

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I apologize for my bad vocabulary. I mean concatenate.

I want D-E-A-D-B-E-E-F instead of getting DEADBEEF

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Scholar jg_bds
Scholar
504 Views
Registered: ‎02-01-2013

Re: AXI Quad SPI FIFOs with Multiple Discrete 8-bit Transfers

Jump to solution

"Discrete 8-bit Transfers" refers to the movement of a single byte in a transaction. (See my definition of a transaction above.) Your interface requires such a transfer, but some don't.  SPI interfaces with some EEPROMs, for example, allow long transfers of bytes in a single transaction--effectively 'bursting' data across the interface. PG153, in its examples, is distinguishing a scenario where a single byte is being transferred in multiple transactions, as opposed to--for example--a different scenario where multiple bytes are transmitted during a single transaction from the SPI FIFO.

-Joe G.

 

 

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