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Visitor liumxy
Visitor
6,763 Views
Registered: ‎01-09-2013

AXI Stream to Video Out IP core never get locked

I'm working on a Video Design with a Microblaze, a VDMA, a Video In to AXIS IP, an AXIS to Video Out IP and an user IP (with ODDRs).  The Timing signals are detected and generated separately by two VTCs. The whole sysem seems to work well. The only problem is that the outputs of AXIS to Video out core keep 0.

 

I have S2MM using tuser as FSYNC, MM2S in free run mode, Video out core in slave mode.  Below is part of the MHS file.

BEGIN axi_vdma
 PARAMETER INSTANCE = axi_vdma_0
 PARAMETER HW_VER = 5.04.a
 PARAMETER C_NUM_FSTORES = 10
 PARAMETER C_USE_FSYNC = 3
 PARAMETER C_DYNAMIC_RESOLUTION = 0
 PARAMETER C_M_AXI_MM2S_DATA_WIDTH = 128
 PARAMETER C_M_AXIS_MM2S_TDATA_WIDTH = 24
 PARAMETER C_MM2S_MAX_BURST_LENGTH = 64
 PARAMETER C_M_AXI_S2MM_DATA_WIDTH = 128
 PARAMETER C_S_AXIS_S2MM_TDATA_WIDTH = 24
 PARAMETER C_S2MM_MAX_BURST_LENGTH = 64
 PARAMETER C_FLUSH_ON_FSYNC = 3
 PARAMETER C_MM2S_GENLOCK_MODE = 3
 PARAMETER C_S2MM_GENLOCK_MODE = 2
 PARAMETER C_BASEADDR = 0x7e200000
 PARAMETER C_HIGHADDR = 0x7e20ffff
 PARAMETER C_INCLUDE_MM2S_DRE = 1
 PARAMETER C_INCLUDE_S2MM_DRE = 1
 BUS_INTERFACE S_AXI_LITE = axi4lite_0
 BUS_INTERFACE M_AXI_MM2S = axi4_0
 BUS_INTERFACE M_AXI_S2MM = axi4_0
 BUS_INTERFACE M_AXIS_MM2S = axi_vdma_0_M_AXIS_MM2S
 BUS_INTERFACE S_AXIS_S2MM = v_vid_in_axi4s_0_M_AXIS_VIDEO
 PORT s_axi_lite_aclk = clk_100_0000MHzMMCM0
 PORT m_axi_mm2s_aclk = clk_200_0000MHzMMCM0
 PORT m_axi_s2mm_aclk = clk_200_0000MHzMMCM0
 PORT s2mm_introut = axi_vdma_0_s2mm_introut
 PORT mm2s_introut = axi_vdma_0_mm2s_introut
 PORT m_axis_mm2s_aclk = net_vid_in
 PORT s_axis_s2mm_aclk = net_vid_in
 PORT mm2s_fsync_out = axi_vdma_0_mm2s_fsync_out
 PORT s2mm_frame_ptr_out = axi_vdma_0_s2mm_frame_ptr_out
 PORT mm2s_frame_ptr_in = axi_vdma_0_s2mm_frame_ptr_out
 PORT s2mm_fsync_out = axi_vdma_0_s2mm_fsync_out
 PORT s2mm_fsync = axi_vdma_0_s2mm_fsync_out
END

BEGIN v_axi4s_vid_out
 PARAMETER INSTANCE = v_axi4s_vid_out_0
 PARAMETER HW_VER = 2.01.a
 PARAMETER VTG_MASTER_SLAVE = 0
 BUS_INTERFACE S_AXIS_VIDEO = axi_vdma_0_M_AXIS_MM2S
 BUS_INTERFACE VTIMING_IN = v_tc_0_VTIMING_OUT
 PORT aresetn = proc_sys_reset_0_Interconnect_aresetn
 PORT video_de = v_axi4s_vid_out_0_video_de
 PORT video_vsync = v_axi4s_vid_out_0_video_vsync
 PORT video_hsync = v_axi4s_vid_out_0_video_hsync
 PORT video_data = v_axi4s_vid_out_0_video_data
 PORT vtg_ce = v_axi4s_vid_out_0_vtg_ce
 PORT locked = v_axi4s_vid_out_0_locked
 PORT rst = net_gnd
 PORT aclken = net_vcc
 PORT aclk = net_vid_in
 PORT video_out_clk = net_vid_in
END

BEGIN v_vid_in_axi4s
 PARAMETER INSTANCE = v_vid_in_axi4s_0
 PARAMETER HW_VER = 2.01.a
 BUS_INTERFACE M_AXIS_VIDEO = v_vid_in_axi4s_0_M_AXIS_VIDEO
 BUS_INTERFACE VTIMING_OUT = v_vid_in_axi4s_0_VTIMING_OUT
 PORT vid_de = v_vid_in_axi4s_0_vid_de
 PORT vid_vsync = v_vid_in_axi4s_0_vid_vsync
 PORT vid_hsync = v_vid_in_axi4s_0_vid_hsync
 PORT vid_data = v_vid_in_axi4s_0_vid_data
 PORT aclk = clk_200_0000MHzMMCM0
 PORT aresetn = proc_sys_reset_0_Interconnect_aresetn
 PORT vid_in_clk = net_vid_in
 PORT rst = net_gnd
 PORT aclken = net_vcc
END

//VTC Generator
BEGIN v_tc
 PARAMETER INSTANCE = v_tc_0
 PARAMETER HW_VER = 5.01.a
 PARAMETER C_GEN_VIDEO_FORMAT = 2
 PARAMETER C_SYNC_EN = 0
 PARAMETER C_GEN_F0_VSYNC_VSTART = 725
 PARAMETER C_GEN_F0_VSYNC_VEND = 730
 PARAMETER C_DETECT_EN = 0
 PARAMETER C_BASEADDR = 0x7b400000
 PARAMETER C_HIGHADDR = 0x7b40ffff
 BUS_INTERFACE S_AXI = axi4lite_0
 BUS_INTERFACE VTIMING_OUT = v_tc_0_VTIMING_OUT
 PORT s_axi_aclk = clk_100_0000MHzMMCM0
 PORT gen_clken = v_axi4s_vid_out_0_vtg_ce
 PORT fsync_out = v_tc_0_fsync_out
 PORT s_axi_aclken = net_vcc
 PORT resetn = net_vcc
 PORT clken = net_vcc
 PORT clk = net_vid_in
END

//VTC Detector
BEGIN v_tc
 PARAMETER INSTANCE = v_tc_1
 PARAMETER HW_VER = 5.01.a
 PARAMETER C_GENERATE_EN = 0
 PARAMETER C_DETECT_EN = 1
 PARAMETER C_BASEADDR = 0x7b420000
 PARAMETER C_HIGHADDR = 0x7b42ffff
 PARAMETER C_DET_VBLANK_EN = 0
 PARAMETER C_DET_HBLANK_EN = 0
 BUS_INTERFACE S_AXI = axi4lite_0
 BUS_INTERFACE VTIMING_IN = v_vid_in_axi4s_0_VTIMING_OUT
 PORT s_axi_aclk = clk_100_0000MHzMMCM0
 PORT clk = net_vid_in
 PORT s_axi_aclken = net_vcc
 PORT resetn = net_vcc
 PORT clken = net_vcc
 PORT det_clken = net_vcc
END

 

  

 

 

 

 

Tags (3)
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6 Replies
Visitor liumxy
Visitor
6,762 Views
Registered: ‎01-09-2013

Re: AXI Stream to Video Out IP core never get locked

chipscope

 

Any  suggestion is appreciated. Thank you!

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Visitor liumxy
Visitor
6,761 Views
Registered: ‎01-09-2013

Re: AXI Stream to Video Out IP core never get locked

Here is part of my C code in SDK. Interrputs of  S2MM and MM2S are also enabled but the code is not listed below. 

   //vtc 
    XVtc AxiVtcIn, AxiVtcOut;

    XVtc_Config *AxiVtc_Config;
    XVtc_SourceSelect src;
    XVtc_Polarity pol;
    XVtc_Signal sig;

	AxiVtc_Config = XVtc_LookupConfig(XPAR_VTC_0_DEVICE_ID);
    XVtc_CfgInitialize(&AxiVtcOut, AxiVtc_Config, AxiVtc_Config->BaseAddress);

	AxiVtc_Config = XVtc_LookupConfig(XPAR_VTC_1_DEVICE_ID);
	XVtc_CfgInitialize(&AxiVtcIn, AxiVtc_Config, AxiVtc_Config->BaseAddress);

	//source select: 1, Generator Registers are source; 0 Detector
	src.HSyncPolsrc=1;
	src.HBlankPolsrc=1;
	src.HBackPorchsrc=1;
	src.HFrontPorchsrc=1;
	src.HSyncsrc=1;
	src.HActivesrc=1;
	src.HTotalsrc=1;

	src.VSyncPolsrc=1;
	src.VBlankPolsrc=1;
	src.VBackPorchsrc=1;
	src.VFrontPorchsrc=1;
	src.VSyncsrc=1;
	src.VActivesrc=1;
	src.VTotalsrc=1;

	//polarity, active high
	pol.HBlankPol=1;
	pol.HSyncPol=1;
	pol.VBlankPol=1;
	pol.VSyncPol=1;

	//set Video Parameters, 720p
	sig.HActiveStart=0;
	sig.HFrontPorchStart=1280;
	sig.HSyncStart=1390;
	sig.HBackPorchStart=1430;
	sig.HTotal=1650;
	sig.V0ActiveStart=0;
	sig.V0FrontPorchStart=720;
	sig.V0SyncStart=724;
	sig.V0BackPorchStart=729;
	sig.V0Total=750;

	//write to HW
	XVtc_SetPolarity(&AxiVtcOut, &pol);
	XVtc_SetGenerator(&AxiVtcOut, &sig);
	XVtc_SetSource(&AxiVtcOut, &src);
	XVtc_Enable(&AxiVtcOut, 1);
	XVtc_Enable(&AxiVtcIn, 2);
}


       //VDMA 
       Config = XAxiVdma_LookupConfig(DMA_DEVICE_ID);

       /* Initialize DMA engine */
       XAxiVdma_CfgInitialize(&AxiVdma, Config, Config->BaseAddress);

       XAxiVdma_SetFrmStore(&AxiVdma, NUMBER_OF_READ_FRAMES, XAXIVDMA_READ);

        XAxiVdma_SetFrmStore(&AxiVdma, NUMBER_OF_WRITE_FRAMES, XAXIVDMA_WRITE);
        FrameCfg.ReadFrameCount = NUMBER_OF_READ_FRAMES;
	FrameCfg.WriteFrameCount = NUMBER_OF_WRITE_FRAMES;
	FrameCfg.ReadDelayTimerCount = DELAY_TIMER_COUNTER;
	FrameCfg.WriteDelayTimerCount = DELAY_TIMER_COUNTER;

	XAxiVdma_SetFrameCounter(&AxiVdma, &FrameCfg);

        
        //MM2S
        ReadCfg.VertSizeInput = FRAME_HORIZONTAL_LEN;
	ReadCfg.HoriSizeInput = FRAME_VERTICAL_LEN;

	ReadCfg.Stride = FRAME_HORIZONTAL_LEN;
	ReadCfg.FrameDelay = 0;  

	ReadCfg.EnableCircularBuf = 1;

	ReadCfg.EnableFrameCounter = 0; /* Endless transfers */

	ReadCfg.FixedFrameStoreAddr = 0; /* We are not doing parking */

	XAxiVdma_DmaConfig(InstancePtr, XAXIVDMA_READ, &ReadCfg);

	Addr = READ_ADDRESS_BASE ;
	for(Index = 0; Index < NUMBER_OF_READ_FRAMES; Index++) {
		ReadCfg.FrameStoreStartAddr[Index] = Addr;

		Addr += FRAME_HORIZONTAL_LEN * FRAME_VERTICAL_LEN;
	}

	XAxiVdma_DmaSetBufferAddr(InstancePtr, XAXIVDMA_READ,
			ReadCfg.FrameStoreStartAddr);

       //S2MM
       WriteCfg.VertSizeInput = FRAME_HORIZONTAL_LEN;
       WriteCfg.HoriSizeInput = FRAME_VERTICAL_LEN;

	WriteCfg.Stride = FRAME_HORIZONTAL_LEN;
	WriteCfg.FrameDelay = 0;  

	WriteCfg.EnableCircularBuf = 1;

	WriteCfg.EnableFrameCounter = 0; /* Endless transfers */

	WriteCfg.FixedFrameStoreAddr = 0; /* We are not doing parking */

	XAxiVdma_DmaConfig(InstancePtr, XAXIVDMA_WRITE, &WriteCfg);

	Addr = WRITE_ADDRESS_BASE;
	for(Index = 0; Index < NUMBER_OF_WRITE_FRAMES; Index++) {
		WriteCfg.FrameStoreStartAddr[Index] = Addr;

		Addr += FRAME_HORIZONTAL_LEN * FRAME_VERTICAL_LEN;
	}

	XAxiVdma_DmaSetBufferAddr(InstancePtr, XAXIVDMA_WRITE,
	        WriteCfg.FrameStoreStartAddr);
       
        XAxiVdma_DmaStart(InstancePtr, XAXIVDMA_WRITE);
        XAxiVdma_DmaStart(InstancePtr, XAXIVDMA_READ);
        
        XAxiVdma_FsyncSrcSelect(&AxiVdma, XAXIVDMA_S2MM_TUSER_FSYNC, XAXIVDMA_WRITE);


 

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Visitor liumxy
Visitor
6,756 Views
Registered: ‎01-09-2013

Re: AXI Stream to Video Out IP core never get locked

Below is some register values of VTCs.

 

--- Entering main() --- 
generator active size = 2D00500
generator error = 0
generator status register = 13200
detector control register = 1
detector active size = 2D00500
detector hsync = 596056E
detector vsync = 2D902D4
detector hsize = 672
detector vsize = 2EE
--- Exiting main() ---

 

The picture of Chipscope turns out to be tuny. It is attached here. Thank you for any help.

3010.png
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Visitor liumxy
Visitor
6,726 Views
Registered: ‎01-09-2013

Re: AXI Stream to Video Out IP core never get locked

Is there anyone can help? Any Suggestion is appreciated.

 

Here is a summary of the configuration.

VDMA:

- S2MM use tuser as FSYNC,  MM2S in free run mode.

- Genlock enabled. S2MM is dynamic master, MM2S is dynamic slave.

- Stream data width 24, Memory map data width 128

- DRE enabled.

VTC1 as Detector

- AXILITE-interface enabled.

 

VTC0 asGenerator 

- AXILITE - interface enabled.

- generation of all Sync and Blanking signals enabled, chroma not enabled.

- 720p RGB as default setting. 

- Frame Sync horizontal start is 0, vertical start is 0.

 

AXI Stream Video out core

- slave mode

- RGB format

 

Some Connections

- vtg_ce of axis_vid_out connected with gen_clken of VTC0 Generator.

- Video in and Video out AXI stream interface use the same clock signal, i.e. clock input from FMC.

 

Please give some information. Thank you!

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Visitor liumxy
Visitor
6,724 Views
Registered: ‎01-09-2013

Re: AXI Stream to Video Out IP core never get locked

names of register values of VTCs above is not clear.

 

--- Entering main() --- 
generator active size = 2D00500 (720p)
generator error = 0
generator status register = 13200 (LOCK_LOSS bit asserted)
detector control register = 1
detector active size = 2D00500  (720p)
detector hsync start and end = 596056E (1390 1430)
detector vsync start and end = 2D902D4 (724 729)
detector hsize = 672 (1650)
detector vsize = 2EE (750)
--- Exiting main() ---

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Visitor manfield
Visitor
5,910 Views
Registered: ‎02-22-2013

Re: AXI Stream to Video Out IP core never get locked

Hi liumxy,

I've come across the same problem.  AXIS_VID_OUT cannot get locked.

Have u got the solution?

 

 

ZHU

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