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Participant svenssonjoel
Participant
4,226 Views
Registered: ‎03-17-2016

AXI interconnect overloaded? Or deadlock? or ...

Hello, 

 

This is closely related to my previous questions in: 

https://forums.xilinx.com/t5/Zynq-All-Programmable-SoC/Correct-protocol-for-starting-and-restarting-over-and-over-again/td-p/703164

 

But I will try to be more precise in my description this time.  

Hardware tested on: Zynq 7020 (ZedBoard) and Zynq 7010 (Zynqberry) 

 

I have 4 IP blocks connected via a "axi_mem_intercon" to HP port 0. This is for the IP blocks memory accesses. 

The s_axi_control of these IP blocks are connected via an "processing_system7_0_axi_periph" to M_AXI_GP0 for programming

(starting, stopping, reading status). 

 

The IP Block is essentially loop that copies data from one place in memory to another.  It does nothing else. Just read a word then 

write a word, over and over again. 

 

Now as I start these IP blocks, repeatedly, from a loop running on one of the arm cores, there seems to be something that 

causes the IPs to be unresponsive. At this time reading the ctrl registers return 1 and this is a state that the IPs do not leave. 

 

So the program that starts the IPS is essentially 

 

while (work left to do) {

  find idle IP to start

}

 

which should mean that all these 4 IPs would be running simultaneously and each of them issues "tonnes" of reads and writes 

over the men_interconnect. 

  

Now, I am very curious to see if someone knows what is happening here. I have found a tweak that seems to make the 

problem go away, but I am interested in knowing and understanding the causes. The "fix" I found was to 

change the slave and master interfaces on the "axi_mem_intercon" block to use 512 deep packet more FIFOs (32 deep did not resolve it) (tested on a ZedBoard). 

 

 

Any thoughts on this is greatly appreciated. 

 

Thank you very much and have a great day

 

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