03-03-2017 01:49 AM
In AXI4-lite read access, the Master first notifies the read address to the Slave trhough araddr and the handshake involving arvalid and arraedy. Then the Slave fetches the required data and presents it to the Master on rdata, with rvalid signaling the available data and handshake with rready.
The question is: how much time can spend the Slave to fetch the data? in most of the vaweforms I see aroud, the Slave is able to present the required data even at the same cycle when it raises arready (i.e., when it latches the address). However, in my design this latency is variable and can be between 10 and 1024 clock cycles (by design).
I guess that in doing so, I am locking the Master to wait for the Slave, which is not particularly nice. Before considering different design approaches I would like to know if there is a minimum/suggested/maximum latency spec for the Slave to present data.
Thank in advance to the Community!
03-03-2017 09:25 PM
@mrovin in axi there is no limit on how long any ready can take after a valid. There is also no concept of time-out in general. In most processors (zynq or MB), the processor master waits indefinitely. In zynq-mpsoc, there is a time-out module in the built-in interconnects.
Depending on whether your block supports multiple overlapping reads, I would suggest implementing an axi-full interface so that you can allow master(s) to submit multiple reads with long latencies.
03-06-2017 12:51 AM
@muzaffer thank you very much for your reply. Can you address to me any specification document about AXI transactions? This would be really useful.
Regarding your proposal of switching to full AXI4, unfortunately I have to stick to AXI3-lite for my interfaces. Fortunately, the worst-case latency of 1024 cycles is rather unlikely, while the design can provide read data within 8-10 clock cycles.
Thank you again for your help!
03-06-2017 12:56 AM