07-16-2015 01:23 PM
07-16-2015 03:22 PM
07-17-2015 09:52 AM
My IP does logical AND function. And yes, it can set a value to 1 and 0. Is there a way to access GPIO LEDs without specfying the AXI_GPIO IP? If not, is there a possibility to access other LEDs on the board?
07-17-2015 05:24 PM
07-20-2015 08:44 AM
In sysgen, I created the IP. It just consists of logical-AND block. Sysgen provides us with the facility of generating IP, which can be added to the IP catalog of Vivado. Yes, it is in Verilog.
AXI_GPIO Ip is already available in the IP catalog of Vivado. No, I added AXI_GPIO IP beacuse it is the only way to access the GPIO LEDs.
My concern is I am unable to access GPIO LEDs without using AXI_GPIO IP. Is there a way to access the LEDs without instantiating AXI_GPIO IP?
07-20-2015 10:58 AM
07-21-2015 05:55 PM
I've attached the picture with this mail.
My main concern is, how to connect 'pin_input[3:0]' to 'dip_switches_4bits'(GPIO), and 'pin_output[3:0]' to 'led_4bits'(GPIO), without instantiating the AXI GPIO IPs. And also able to access them using SDK.
07-21-2015 06:48 PM
07-22-2015 10:05 PM
I was able to connect the pins with LEDs and dip switches, without using AXI GPIO IP block.
Can you please let me know if there is a procedure to access/control these pins in Xilinx SDK?
07-22-2015 10:18 PM
07-28-2015 09:46 PM
Can you please provide more information on this. From the address editor, I got to know that the offset address is 0x43C0_0000 and high address is 0x43C0_FFFF, but I am unable to program these pins. Is it possible to provide any tutorial on this.
07-29-2015 05:11 PM
08-02-2015 06:36 PM
I created shared_memory IP in sysgen. 'Push_data' and 'Push_write' are the ports connected to GPIO push buttons on ZC706, and 'LED' to GPIO LEDs. The functionality of this design is, whenever I tap both the push buttons, LEDs should blink. This is done using block memory generator. The control and data signals of the block memory generator are connected to the shared memory IP. I think the remaining block design is self-explanatory.
And also I am experiencing the below issue. Could you also please look into this.
01-19-2016 05:45 AM
How to blink without using AXI_GPIO and SDK code?
I wrote simple blinky module:
`timescale 20ns / 1ps module blinky (A,S); input A; output reg S = 0'b1; reg [31:0] counter = 0'b1; // always @(A) begin always @ (posedge A) begin counter <= counter + 1; if (counter == 1000000) begin counter <= 0; S = ~S; end end endmodule
`timescale 20ns / 1ps module blinkyTestBench(); reg A_t; wire S_t; reg i; blinky blinky_0(A_t, S_t); initial begin for(i=0;i<100;i=i+1) begin A_t <=1; #1; A_t <=0; #1; end end endmodule
Do I must to transform it to custom IP? How to do that? Point me please to any helpful manual?