UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Contributor
Contributor
1,689 Views
Registered: ‎08-13-2017

Axi DMA s2mm transfer problem

Jump to solution

Hello everyone, 

 

I was trying to send data from DDS to the DDR memory using SImpleDMA data transfer method,

 

DDS=> AXI_data_fifo => DMA as shown in image belowBlock_diagram.JPG

Dma is configured as below : 

 

axi_dma_config.JPG

I connected the ILA to see the data at the output of the  FIFO, and obtained data after DMA transfer is printed on the uart terminal : 

Data_in.JPG

 

I observed that only one sample is the same rest all data is different at ILA and the UART terminal for below SDK code.  And after 4 data samples "TREADY" signal goes LOW.

 

 

 #include "xaxidma.h"
 #include "xparameters.h"
 #include "xil_types.h"
 #include "xdebug.h"


 /******************** Constant Definitions **********************************/

 /*
  * Device hardware build related constants.
  */

 #define DMA_DEV_ID                XPAR_AXIDMA_0_DEVICE_ID

 #define MEM_BASE_ADDR                0x01000000

 #define TX_BUFFER_BASE                (MEM_BASE_ADDR + 0x00200000)

 // The example can be extended to feature a larger stream package, but for
 // simplicity it is now set to 0x1
 #define MAX_PKT_LEN                0x08



 #if (!defined(DEBUG))
 extern void xil_printf(const char *format, ...);
 #endif

 XAxiDma AxiDma;


 int main()
 {
         XAxiDma_Config *CfgPtr;
         int Status;
         int Index;
         int *TxBufferPtr;

         xil_printf("\r\nStarting sending data\r\n");

         TxBufferPtr = (int *)TX_BUFFER_BASE;

         /* Initialize the XAxiDma device.
          */
         CfgPtr = XAxiDma_LookupConfig(DMA_DEV_ID);
         if (!CfgPtr) {
                 xil_printf("No config found for %d\r\n", DMA_DEV_ID);
                 return XST_FAILURE;
         }

         Status = XAxiDma_CfgInitialize(&AxiDma, CfgPtr);
         if (Status != XST_SUCCESS) {
                 xil_printf("Initialization failed %d\r\n", Status);
                 return XST_FAILURE;
         }

         if(XAxiDma_HasSg(&AxiDma)){
                 xil_printf("Device configured as SG mode \r\n");
                 return XST_FAILURE;
         }

         /* Disable interrupts, we use polling mode
          */
         XAxiDma_IntrDisable(&AxiDma, XAXIDMA_IRQ_ALL_MASK,XAXIDMA_DEVICE_TO_DMA);



         Xil_DCacheFlushRange((UINTPTR)TxBufferPtr, MAX_PKT_LEN);

		 //Sets up the DMA-To-Device so that data i send.
		 Status = XAxiDma_SimpleTransfer(&AxiDma,(UINTPTR) TxBufferPtr, MAX_PKT_LEN, XAXIDMA_DEVICE_TO_DMA);

		 if (Status != XST_SUCCESS) {
				 return XST_FAILURE;
		 }


		 while (XAxiDma_Busy(&AxiDma,XAXIDMA_DEVICE_TO_DMA)) {} //wait



         xil_printf("\r\nDone sending data\r\n");

                  for(Index = 0; Index < MAX_PKT_LEN; )
                  {

                                  xil_printf("\n\r %x",  TxBufferPtr[Index]);
//                                  TxBufferPtr=TxBufferPtr+1;
                                  Index = Index+1;
                  }





         return XST_SUCCESS;
 }

Please give me suggestion, how I can do data transfer correctly.

0 Kudos
1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
1,630 Views
Registered: ‎10-04-2016

Re: Axi DMA s2mm transfer problem

Jump to solution

Hi @amitlwaghmare,

The issue is with the handling of TLAST between the AXI4-Stream Data Fifo and AXI DMA.

 

TLAST is used to signify the end of a streaming data packet. In your waveform, TLAST is always asserted. This means that each data packet is one transfer long. 

 

In an S2MM transfer, AXI DMA moves transfers from from the streaming side to the memory mapped side until is sees TLAST assert. You can set S2MM_LENGTH to indicate a transfer of many more bytes, but once AXI DMA sees TLAST, that means the simple mode transfer is done and you need to reprogram AXI DMA to do another transfer. 

 

AXI DMA has a small buffer in it where it will take in a few additional streaming data transfers. This is why you see it accept a few more data beats before it drops TREADY. If you re-armed the S2MM engine, you would see the next dword from the stream side get written on the memory mapped side.

 

To change when TLAST asserts, you need to add at IP like the AXI4-Stream Subset Converter. You could configure this IP so TLAST asserts only on the 10th transfer (for example) on the AXI4-Stream interface. This would allow 40 Bytes of data to come to the memory mapped side on a single Simple DMA transaction.

 

Regards,

 

Deanna

 

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

1 Reply
Xilinx Employee
Xilinx Employee
1,631 Views
Registered: ‎10-04-2016

Re: Axi DMA s2mm transfer problem

Jump to solution

Hi @amitlwaghmare,

The issue is with the handling of TLAST between the AXI4-Stream Data Fifo and AXI DMA.

 

TLAST is used to signify the end of a streaming data packet. In your waveform, TLAST is always asserted. This means that each data packet is one transfer long. 

 

In an S2MM transfer, AXI DMA moves transfers from from the streaming side to the memory mapped side until is sees TLAST assert. You can set S2MM_LENGTH to indicate a transfer of many more bytes, but once AXI DMA sees TLAST, that means the simple mode transfer is done and you need to reprogram AXI DMA to do another transfer. 

 

AXI DMA has a small buffer in it where it will take in a few additional streaming data transfers. This is why you see it accept a few more data beats before it drops TREADY. If you re-armed the S2MM engine, you would see the next dword from the stream side get written on the memory mapped side.

 

To change when TLAST asserts, you need to add at IP like the AXI4-Stream Subset Converter. You could configure this IP so TLAST asserts only on the 10th transfer (for example) on the AXI4-Stream interface. This would allow 40 Bytes of data to come to the memory mapped side on a single Simple DMA transaction.

 

Regards,

 

Deanna

 

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post