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Explorer
Explorer
8,845 Views
Registered: ‎07-17-2014

Best Method for AXI-Lite interface to PL-FIFO interface

I have a design with a Slave AXI-lite interface that needs to transfer data from a PL FIFO to the PS.

 

The FIFO has the usual CLOCK and EN inputs to handle talking to a processor interface.

 

When I used these FIFOs in the past, the ARM MCU was external and I could throw wait states (I hated them though) into the transaction while I went and got the data from the FIFO.

 

AXI is new for me -- and eventually I'd like to this core to AXI (full) but in the meantime, what's the best way to get the data out of the FIFO onto the AXI data bus.


links to Examples or Documentation would be fabulous. (and yes, I've looked at what I believe to be all the Xilinx docs covering the topic.)

(I see the examples for the AXI Slave, but they really only deal with a register that's defined/kept inside the slave module. The examples don't really cover dealing with external memory devices like a FIFO where clocking/enabling is involved.)

Thanks,

 

 -Ben

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2 Replies
Scholar austin
Scholar
8,839 Views
Registered: ‎02-27-2008

Re: Best Method for AXI-Lite interface to PL-FIFO interface

Have you looked at:

 

http://www.xilinx.com/products/intellectual-property/axi_fifo.html

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Explorer
Explorer
8,824 Views
Registered: ‎07-17-2014

Re: Best Method for AXI-Lite interface to PL-FIFO interface

Hi Austin,

Yes. I looked at the AXI IP FIFOs and they are massive overkill.

For one, this design already has a kernel driver and main application from previous non-ARM/AXI designs.

Additionally, the FIFOs in the design are unidirectional and only 14-15bits wide.

Would you have any suggestions for docs on getting a standard IP FIFO working inside an AXI slave?

Thanks,

-Ben
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