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Visitor steve77
Registered: ‎06-28-2017

Best way to interface with AXI Stream core

OK so I dont  want to use Zynq or some other embedded processor - and want to use an IP core that has AXI streaming interface.


I need a something that will

TRANSMIT:) pull data out of a NATIVE fifo or dual part memory and convert it to streaming master 

RECEIVE:) take a axi stream slave and pump it into a NATIVE fifo or dual part memory so i can read out of NATIVE interface  



there has got to be a simple way to do this - 

I looked at  the following :

1)  [custom logic that moves my data to/from axi_lite] => [axi streaming fifo core  ]  (stream)

2)  [custom logic that moves my data to/from axi_lite] => [axi  data mover core ]   (stream)



If the silly cores weren't encrypted it would be a snap to snip away all the AXI crap and drive the interface directy.




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Registered: ‎11-09-2015

Re: Best way to interface with AXI Stream core

HI @steve77,


If you want a template for IPs with AXI interfaces, create a new IP in vivado:

1. Tool > Create and package a new IP

2. Select create new AXI4 peripheral

3. Add the required interface (for example AXI-Lite master)

4. edit the IP

-> This will create a template you can use for an AXI interface (full/lite or stream)


Hope that helps,





Product Application Engineer - Xilinx Technical Support EMEA
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