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Adventurer
Adventurer
7,147 Views
Registered: ‎02-19-2016

Block Memory Generator in IP Packager

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Hello All,

 

Vivado 2015.2

Block Memory Generator v8.2

Zynq zc706 eval board

 

I used Vivado's block memory generator to create a native single port ram.  I'm trying to include the BRAM in an IP block I created that contains all my PL code.  I am able to simulate and synthesize ok, however when I implement the design the BRAM is optimized out.  Due to company restrictions I cannot upload my design, but I believe I may not be including the files in IP packager correctly.  In IP packager I have included the files for VHDL synthesis in this order:

ip/RAM_40x262144/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2_vhsyn_rfs.vhd (on a side note can anyone explain what this file is?)

ip/RAM_40x262144/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2.vhd

ip/RAM_40x262144/synth/RAM_40X262144.vhd

 

I also tried inluding the .xci file, but I had the same issue so I removed it.

 

In synthesis, I see the warning below, however I see the same warning in the example design so I'm not too concerned:

WARNING: [Synth 8-312] ignoring unsynthesizable construct: assertion statement [c:/Data/Project/sources_1/ip/RAM_40X262144/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2_vhsyn_rfs.vhd:4793]

 

In implementation I see the Info:

[Opt 31-120] Instance Project_TOP/U0 (blk_mem_gen_v8_2_blk_mem_gen_v8_2) has been optimized to an empty box cell during sweep but it has constraints that prevent its removal. Empty box cells do not impact the implementation flow but they have no functional relevance.

 

Anyone know why Vivado is optimizing out my BRAM?

 

Thanks!

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Adventurer
Adventurer
13,351 Views
Registered: ‎02-19-2016

Re: Block Memory Generator in IP Packager

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Thanks for the response Deepika.

 

Yes, I can see the rest of the packaged design is being implemented and yes I have connected the I/O to the RAM appropriately.

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3 Replies
Xilinx Employee
Xilinx Employee
7,107 Views
Registered: ‎09-20-2012

Re: Block Memory Generator in IP Packager

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Hi @zoppina

 

Did the Implementation go through in the IP packager project?

 

Have you properly connected the BMG IP inputs and outputs?

Thanks,
Deepika.
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Adventurer
Adventurer
13,352 Views
Registered: ‎02-19-2016

Re: Block Memory Generator in IP Packager

Jump to solution

Thanks for the response Deepika.

 

Yes, I can see the rest of the packaged design is being implemented and yes I have connected the I/O to the RAM appropriately.

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Adventurer
Adventurer
6,805 Views
Registered: ‎02-19-2016

Re: Block Memory Generator in IP Packager

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My apologies, but actually my douta was not connected properly.  The issue is resolved.  Thanks for the help.

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