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Adventurer
Adventurer
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Registered: ‎05-12-2016

Bypass AXI Stream module

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Hi

I need the capability to bypass certain AXI stream modules. For example, I instantiate a FIR Compiler on my block diagram. This receives an input, filters the signal digitally, and outputs the result, which is passed on to further processing stages and finally is transmitted via DMA to the processor.

However, I require the ability to switch off this filter, so that it simply works as a signal bypass (I'm tolerant to whichever latency this could cause).

The FIR Compiler doesn't have a "bypass" or "enable" pin or configuration, so I was thinking: is there a module that do what I want? It should receive AXIS input and multiplex its output to either a) FIR Compiler input or b) Fir Compiler Output.

The first job I believe is feasible, as it's just a matter of multiplexing my output to one of the hypoteticals M00 or M01. However, I can not connect my next stage's slave port to either the output of the FIR Compiler or the output of my bypass system.

Is there something that solves this, I believe, quite common case?

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Highlighted
152 Views
Registered: ‎06-21-2017

Re: Bypass AXI Stream module

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Two solutions to consider.  Write a AXI Stream multiplexer in your favorite HDL or generate a filter with two sets of coefficients.  Make one of the sets a bypass, that is one coefficient is full scale and the rest zero.

View solution in original post

1 Reply
Highlighted
153 Views
Registered: ‎06-21-2017

Re: Bypass AXI Stream module

Jump to solution

Two solutions to consider.  Write a AXI Stream multiplexer in your favorite HDL or generate a filter with two sets of coefficients.  Make one of the sets a bypass, that is one coefficient is full scale and the rest zero.

View solution in original post