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Visitor odedyer
Visitor
4,897 Views
Registered: ‎09-04-2016

Can there be an error when writing from PL to PS DDR?

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Hi,

 

I am using a few AXI masters (generated by "Create and package IP --> Create AXI4 Peripheral"), connected via one AXI interconnect to one of the PS HP ports.

 

After writing, the master performs validation by reading from the same address and comparing to the written value, and if there's a mismatch an error strobe is raised.

My question is - should there ever be such error? If so, what would be a good mechanism to make sure the value is eventually written? Is there a chance that I will be stuck retrying the write forever?

 

Thanks!

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Historian
Historian
9,482 Views
Registered: ‎01-23-2009

Re: Can there be an error when writing from PL to PS DDR?

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No hardware is perfect - ever. There are a large number of extremely low probability (and essentially) random mechanisms that can corrupt digital systems. Some parts of the system are more or less susceptible to these errors.

 

High speed signalling is a place that is more susceptible - the high speed data on a DDRx interface is "relatively" high. That being said, it is still extremely reliable - errors are expected to occur, but once in every 10^x operations, where x is pretty large. The value will depend on a lot of factors, of which the quality of your board layout and power supplies are a few, as well as the frequency of the DDRx devices and the speed you are running them at. But even moderately well designed interfaces would expect N>15 maybe even 20. So, you would expect to get errors VERY VERY infrequently.

 

But even infrequent at these frequencies means "occasionally". This is the reason that some memory systems use parity bits (for error checking) and even error protection codes - these protect not only against corruption on the busses to and from the DDRx memory, but also errors that occur within the memory (which can also happen).

 

All this being said, "validating" data as you write it is probably not all that useful. First of all, the probability of an error is so small that using half your bandwidth to check it is overkill. Furthermore, the probability of failure on the readback that is validating it is just as high as the probability of an error during writing it. Lastly, none of this protects against errors induced in the RAM itself as the data sits in the RAM (Single Event Upsets or SEUs).

 

"Is there a chance that it will be stuck retrying the write forever" - theoretically, yes. But the probability is (I was going to use the term "infinitely small", but that doesn't even begin to cover it). Lets say the chance of an error is 10^-15. Two in a row is 10^-30. So assuming you are doing 2.4x10^9 operations per second (2.4Gbps is around the top for current DDR3), you would expect two back to back errors to occur roughly once in 4x10^20 seconds. For reference the age of the universe (time since the big bang) is 4x10^17 seconds (so you probably don't need to worry about it!)

 

Avrum

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2 Replies
Historian
Historian
9,483 Views
Registered: ‎01-23-2009

Re: Can there be an error when writing from PL to PS DDR?

Jump to solution

No hardware is perfect - ever. There are a large number of extremely low probability (and essentially) random mechanisms that can corrupt digital systems. Some parts of the system are more or less susceptible to these errors.

 

High speed signalling is a place that is more susceptible - the high speed data on a DDRx interface is "relatively" high. That being said, it is still extremely reliable - errors are expected to occur, but once in every 10^x operations, where x is pretty large. The value will depend on a lot of factors, of which the quality of your board layout and power supplies are a few, as well as the frequency of the DDRx devices and the speed you are running them at. But even moderately well designed interfaces would expect N>15 maybe even 20. So, you would expect to get errors VERY VERY infrequently.

 

But even infrequent at these frequencies means "occasionally". This is the reason that some memory systems use parity bits (for error checking) and even error protection codes - these protect not only against corruption on the busses to and from the DDRx memory, but also errors that occur within the memory (which can also happen).

 

All this being said, "validating" data as you write it is probably not all that useful. First of all, the probability of an error is so small that using half your bandwidth to check it is overkill. Furthermore, the probability of failure on the readback that is validating it is just as high as the probability of an error during writing it. Lastly, none of this protects against errors induced in the RAM itself as the data sits in the RAM (Single Event Upsets or SEUs).

 

"Is there a chance that it will be stuck retrying the write forever" - theoretically, yes. But the probability is (I was going to use the term "infinitely small", but that doesn't even begin to cover it). Lets say the chance of an error is 10^-15. Two in a row is 10^-30. So assuming you are doing 2.4x10^9 operations per second (2.4Gbps is around the top for current DDR3), you would expect two back to back errors to occur roughly once in 4x10^20 seconds. For reference the age of the universe (time since the big bang) is 4x10^17 seconds (so you probably don't need to worry about it!)

 

Avrum

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Visitor odedyer
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4,843 Views
Registered: ‎09-04-2016

Re: Can there be an error when writing from PL to PS DDR?

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Great answer, and  was even fun to read. Thanks! :)

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