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Adventurer
Adventurer
5,666 Views
Registered: ‎02-12-2015

Clock buf regions implementation error

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Hi,

 

I have a Vivado (2014.4) design using the SelectIO Interface Wizard block to deserialize camera link data.

 

In the design I have an AXI peripheral which samples the camera data, a zynq processor and a dma block. I was trying to use the clock div output of the SelectIO block to drive the axi clocks of my axi peripheral, dma and zynq blocks.

 

However, I get a placer error when I run implementation - 

 

[Place 30-458] The loads of regional clock BUF (BUFR) instance 'design_1_i/selectio_wiz_0/U0/clkout_buf_inst' are locked in multiple clock regions. A BUFR can drive loads in only one clock region.

 

I was hoping for some advice - should I look at using a different clock source for the AXI blocks? One of the Zynq clocks?

 

Thanks in advance

 

Marc

 

 

 

cameraLink_placerError.png
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1 Solution

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Scholar trenz-al
Scholar
9,421 Views
Registered: ‎11-09-2013

Re: Clock buf regions implementation error

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as you can see the code generated with wizard is not working..

 

for cameralink RX MMCM is needed, but the wizard connected clock directly this is no go...!

 

 

View solution in original post

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5 Replies
Scholar trenz-al
Scholar
5,655 Views
Registered: ‎11-09-2013

Re: Clock buf regions implementation error

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it is a bit work required as to map the selectiowizard to xxx to get cameralink ip working

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Xilinx Employee
Xilinx Employee
5,651 Views
Registered: ‎09-20-2012

Re: Clock buf regions implementation error

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Hi,

 

What loads is this buffer driving? Open synthesized design and check the loads of the buffer mentioned in the error.

 

It could be that there are location constraints on the loads which is restraining their placement to more than one clock region. If this is the case see if BUFG can be used instead. Else you can use combination of BUFMR and BUFR resources to drive loads in multiple clock regions.

 

Thanks,

Deepika.

Thanks,
Deepika.
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Adventurer
Adventurer
5,618 Views
Registered: ‎02-12-2015

Re: Clock buf regions implementation error

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Hi, thanks for the reply...

 

Here's what I've been able to find - I'm a bit out of my comfort zone here but keen to learn! 

 

 

cameraLink_placerError_clocks.png
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Scholar trenz-al
Scholar
9,422 Views
Registered: ‎11-09-2013

Re: Clock buf regions implementation error

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as you can see the code generated with wizard is not working..

 

for cameralink RX MMCM is needed, but the wizard connected clock directly this is no go...!

 

 

View solution in original post

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Visitor likith
Visitor
661 Views
Registered: ‎01-04-2019

showing I/O clock placer failed during implementation

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[Constraints 18-633] Creating clock design_1_i/pcie4_uscale_plus_1/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/design_1_pcie4_uscale_plus_0_0_gt_i/inst/gen_gtwizard_gthe4_top.design_1_pcie4_uscale_plus_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/TXOUTCLK with 4 sources. ["/home/vvdn/AICI_VAC1_ZYNC/AICI_VAC1_ZYNC.srcs/sources_1/bd/design_1/ip/design_1_pcie4_uscale_plus_0_0/source/ip_pcie4_uscale_plus_x1y0.xdc":118]

 

[Timing 38-3] User defined clock exists on pin design_1_i/pcie4_uscale_plus_0/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/design_1_pcie4_uscale_plus_0_3_gt_i/inst/gen_gtwizard_gtye4_top.design_1_pcie4_uscale_plus_0_3_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK [See "/home/vvdn/AICI_VAC1_ZYNC/AICI_VAC1_ZYNC.srcs/sources_1/bd/design_1/ip/design_1_pcie4_uscale_plus_0_3_1/source/ip_pcie4_uscale_plus_x0y3.xdc":118] and will prevent any subsequent automatic derivation of generated clocks on that pin. If the user defined clock specifies '-add', any existing auto-derived clocks on that pin are retained.

[IP_Flow 19-4830] Duplicate Interface found for 'xilinx.com:display_pcie4_uscaleplus:int_gtcom:1.0'. The one found in location '/home/vvdn/Vivado/2018.2/patches/AR71421_Vivado_2018_2_preliminary_rev1/vivado/data/ip/xilinx/qdma_v2_0/interfaces/pcie4_usp_int_gtcom.xml' will take precedence over the same Interface in location '/home/vvdn/Vivado/2018.2/data/ip/xilinx/xdma_v4_1/interfaces/pcie4_usp_int_gtcom.xml'

 

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