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Explorer
Explorer
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Registered: ‎11-06-2011

Connecting the PLB to the user logic

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Hey guys.

 

I have created the following component

 

COMPONENT Control1
    PORT(
         clk : IN  std_logic;
         rst : IN  std_logic;
         add_data : INOUT  std_logic_vector(15 downto 0);
         ale : IN  std_logic;
         rd : IN  std_logic;
         wr : IN  std_logic;
         Rx_in : IN  std_logic_vector(1 downto 0);
         Tx_out : OUT  std_logic_vector(1 downto 0);
         msborlsb : IN  std_logic
        );
    END COMPONENT;

 

I want to connect the ports

 

         add_data : INOUT  std_logic_vector(15 downto 0);
         ale : IN  std_logic;
         rd : IN  std_logic;
         wr : IN  std_logic;

 

to the PLB, I'm using ppc 440.

 

As for

 

         Rx_in : IN  std_logic_vector(1 downto 0);
         Tx_out : OUT  std_logic_vector(1 downto 0);

 

I want to connect them on some kind of a loop, without using LocalLink Interface.

 

I know I need an interface to connect the PLB and the my user logic.

 

Can I please have some guidelines about how to build that interface?

 

Thanks a lot.

Assaf.

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Explorer
Explorer
9,110 Views
Registered: ‎11-06-2011

Re: Connecting the PLB to the user logic

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Thanks.

 

I'll do that.

View solution in original post

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Moderator
Moderator
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Registered: ‎08-25-2009

Re: Connecting the PLB to the user logic

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Hi Assaf,

 

The PLBv46 IPIF is needed between your user logic and PLBv46 bus. You can use CIP wizard in EDK and create a basic custom IP; and then mofiy the core. After, you can import the core again by using CIP wizard.

 

Thanks,

Nan

"Don't forget to reply, kudo and accept as solution."
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Explorer
Explorer
9,111 Views
Registered: ‎11-06-2011

Re: Connecting the PLB to the user logic

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Thanks.

 

I'll do that.

View solution in original post

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Explorer
Explorer
7,071 Views
Registered: ‎11-06-2011

Re: Connecting the PLB to the user logic

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Do I need to create an IP out of my component in order to use it with the IPIF?

 

COMPONENT Control1
    PORT(
         clk : IN  std_logic;
         rst : IN  std_logic;
         add_data : INOUT  std_logic_vector(15 downto 0);
         ale : IN  std_logic;
         rd : IN  std_logic;
         wr : IN  std_logic;
         Rx_in : IN  std_logic_vector(1 downto 0);
         Tx_out : OUT  std_logic_vector(1 downto 0);
         msborlsb : IN  std_logic
        );
    END COMPONENT;

 

Another thing, I want to use an input fifo and an output fifo, do I need to create registers in the IPIF and then connect those register to the fifos?

 

Thanks a lot.

 

BTW I accidentally pushed the SOLVED button.

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Scholar
Scholar
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Registered: ‎04-07-2008

Re: Connecting the PLB to the user logic

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Hi,

  Have looked at this APP Note XAPP967.

 

It talks about the IPIF.

 

When you use the IPIF fifos it is connected by the Wizard(IPIF) to the PLB bus.

 

The Way to add your design into the IPIF is to instantiate into the User Logic File.  You need to conform

to the IPIF signals.  Look at XAPP967.

 

You don't hook directly to the PLB Bus.  Just hook to the User Logic Interface.

 

Gary

 

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Explorer
Explorer
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Registered: ‎11-06-2011

Re: Connecting the PLB to the user logic

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I'll do that.

 

Thanks.

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Explorer
Explorer
7,048 Views
Registered: ‎11-06-2011

Re: Connecting the PLB to the user logic

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Well, I've created an IPIF, a simple one, it has only one register.

 

The question is, how do I connect it to my design, it's not a simple user logic as in the example, it has many VHDL files...

 

Here is what I've created in the ISE

 

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    17:47:48 12/07/2011
-- Design Name:
-- Module Name:    Top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Top is
    
    PORT(
        fpga_0_RS232_Uart_1_RX_pin : IN std_logic;
        fpga_0_RS232_Uart_2_RX_pin : IN std_logic;
        fpga_0_clk_1_sys_clk_pin : IN std_logic;
        fpga_0_rst_1_sys_rst_pin : IN std_logic;    
        fpga_0_DDR2_SDRAM_DDR2_DQ_pin : INOUT std_logic_vector(63 downto 0);
        fpga_0_DDR2_SDRAM_DDR2_DQS_pin : INOUT std_logic_vector(7 downto 0);
        fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin : INOUT std_logic_vector(7 downto 0);      
        fpga_0_RS232_Uart_1_TX_pin : OUT std_logic;
        fpga_0_RS232_Uart_2_TX_pin : OUT std_logic;
        fpga_0_DDR2_SDRAM_DDR2_A_pin : OUT std_logic_vector(12 downto 0);
        fpga_0_DDR2_SDRAM_DDR2_BA_pin : OUT std_logic_vector(1 downto 0);
        fpga_0_DDR2_SDRAM_DDR2_RAS_N_pin : OUT std_logic;
        fpga_0_DDR2_SDRAM_DDR2_CAS_N_pin : OUT std_logic;
        fpga_0_DDR2_SDRAM_DDR2_WE_N_pin : OUT std_logic;
        fpga_0_DDR2_SDRAM_DDR2_CS_N_pin : OUT std_logic;
        fpga_0_DDR2_SDRAM_DDR2_ODT_pin : OUT std_logic_vector(1 downto 0);
        fpga_0_DDR2_SDRAM_DDR2_CKE_pin : OUT std_logic;
        fpga_0_DDR2_SDRAM_DDR2_DM_pin : OUT std_logic_vector(7 downto 0);
        fpga_0_DDR2_SDRAM_DDR2_CK_pin : OUT std_logic_vector(1 downto 0);
        fpga_0_DDR2_SDRAM_DDR2_CK_N_pin : OUT std_logic_vector(1 downto 0)
        );
        
end Top;

architecture Behavioral of Top is
    
    COMPONENT Control1
    PORT(
        clk : IN std_logic;
        rst : IN std_logic;
        ale : IN std_logic;
        rd : IN std_logic;
        wr : IN std_logic;
        msborlsb : IN std_logic;       
        add_data : INOUT std_logic_vector(15 downto 0)
        );
    END COMPONENT;
    
    COMPONENT system
    PORT(
        fpga_0_RS232_Uart_1_RX_pin : IN std_logic;
        fpga_0_RS232_Uart_2_RX_pin : IN std_logic;
        fpga_0_clk_1_sys_clk_pin : IN std_logic;
        fpga_0_rst_1_sys_rst_pin : IN std_logic;    
        fpga_0_DDR2_SDRAM_DDR2_DQ_pin : INOUT std_logic_vector(63 downto 0);
        fpga_0_DDR2_SDRAM_DDR2_DQS_pin : INOUT std_logic_vector(7 downto 0);
        fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin : INOUT std_logic_vector(7 downto 0);      
        fpga_0_RS232_Uart_1_TX_pin : OUT std_logic;
        fpga_0_RS232_Uart_2_TX_pin : OUT std_logic;
        fpga_0_DDR2_SDRAM_DDR2_A_pin : OUT std_logic_vector(12 downto 0);
        fpga_0_DDR2_SDRAM_DDR2_BA_pin : OUT std_logic_vector(1 downto 0);
        fpga_0_DDR2_SDRAM_DDR2_RAS_N_pin : OUT std_logic;
        fpga_0_DDR2_SDRAM_DDR2_CAS_N_pin : OUT std_logic;
        fpga_0_DDR2_SDRAM_DDR2_WE_N_pin : OUT std_logic;
        fpga_0_DDR2_SDRAM_DDR2_CS_N_pin : OUT std_logic;
        fpga_0_DDR2_SDRAM_DDR2_ODT_pin : OUT std_logic_vector(1 downto 0);
        fpga_0_DDR2_SDRAM_DDR2_CKE_pin : OUT std_logic;
        fpga_0_DDR2_SDRAM_DDR2_DM_pin : OUT std_logic_vector(7 downto 0);
        fpga_0_DDR2_SDRAM_DDR2_CK_pin : OUT std_logic_vector(1 downto 0);
        fpga_0_DDR2_SDRAM_DDR2_CK_N_pin : OUT std_logic_vector(1 downto 0)
        );
    END COMPONENT;

    attribute box_type : string;
    attribute box_type of system : component is "user_black_box";
    
    signal clk : std_logic;
    signal rst : std_logic;
    signal ale : std_logic;
    signal rd : std_logic;
    signal wr : std_logic;
    signal msborlsb : std_logic;       
    signal add_data : std_logic_vector(15 downto 0);

begin
    
    Inst_system: system PORT MAP(
        fpga_0_RS232_Uart_1_RX_pin => fpga_0_RS232_Uart_1_RX_pin,
        fpga_0_RS232_Uart_1_TX_pin => fpga_0_RS232_Uart_1_TX_pin,
        fpga_0_RS232_Uart_2_RX_pin => fpga_0_RS232_Uart_2_RX_pin,
        fpga_0_RS232_Uart_2_TX_pin => fpga_0_RS232_Uart_2_TX_pin,
        fpga_0_DDR2_SDRAM_DDR2_DQ_pin => fpga_0_DDR2_SDRAM_DDR2_DQ_pin,
        fpga_0_DDR2_SDRAM_DDR2_DQS_pin => fpga_0_DDR2_SDRAM_DDR2_DQS_pin,
        fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin => fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin,
        fpga_0_DDR2_SDRAM_DDR2_A_pin => fpga_0_DDR2_SDRAM_DDR2_A_pin,
        fpga_0_DDR2_SDRAM_DDR2_BA_pin => fpga_0_DDR2_SDRAM_DDR2_BA_pin,
        fpga_0_DDR2_SDRAM_DDR2_RAS_N_pin => fpga_0_DDR2_SDRAM_DDR2_RAS_N_pin,
        fpga_0_DDR2_SDRAM_DDR2_CAS_N_pin => fpga_0_DDR2_SDRAM_DDR2_CAS_N_pin,
        fpga_0_DDR2_SDRAM_DDR2_WE_N_pin => fpga_0_DDR2_SDRAM_DDR2_WE_N_pin,
        fpga_0_DDR2_SDRAM_DDR2_CS_N_pin => fpga_0_DDR2_SDRAM_DDR2_CS_N_pin,
        fpga_0_DDR2_SDRAM_DDR2_ODT_pin => fpga_0_DDR2_SDRAM_DDR2_ODT_pin,
        fpga_0_DDR2_SDRAM_DDR2_CKE_pin => fpga_0_DDR2_SDRAM_DDR2_CKE_pin,
        fpga_0_DDR2_SDRAM_DDR2_DM_pin => fpga_0_DDR2_SDRAM_DDR2_DM_pin,
        fpga_0_DDR2_SDRAM_DDR2_CK_pin => fpga_0_DDR2_SDRAM_DDR2_CK_pin,
        fpga_0_DDR2_SDRAM_DDR2_CK_N_pin => fpga_0_DDR2_SDRAM_DDR2_CK_N_pin,
        fpga_0_clk_1_sys_clk_pin => fpga_0_clk_1_sys_clk_pin,
        fpga_0_rst_1_sys_rst_pin => fpga_0_rst_1_sys_rst_pin
    );
    
    Inst_Control1: Control1 PORT MAP(
        clk => clk,
        rst => rst,
        add_data => add_data,
        ale => ale,
        rd => rd,
        wr => wr,
        msborlsb => msborlsb
    );

end Behavioral;

 

This is the Top level.

Most of it is from the system.xmp but it also contain my component.

 

I want to send what I put in the register from the software side, to the add_data port.

What do u suggest should I use for ale, rd and wr?

 

Thanks a lot.

Assaf.

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Scholar
Scholar
7,040 Views
Registered: ‎04-07-2008

Re: Connecting the PLB to the user logic

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Hi,

  Try looking at You Tube videos on this subject.

 

Don't  put the logic in the top level this way. Look at the videos below.  It should help.

 

 

 

http://www.youtube.com/watch?v=MC1amstP_8A&feature=mfu_in_order&list=UL

 

http://www.youtube.com/watch?v=WYOQpqlEY94&feature=related

 

http://www.youtube.com/watch?v=DkjVXeqRKjE&feature=related

 

Gary

 

 

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Explorer
Explorer
7,031 Views
Registered: ‎11-06-2011

Re: Connecting the PLB to the user logic

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Well.

 

I've already seen those...

 

He doesn't have user logic like I do.

 

All he does is to right to a register.

 

Then how should I put my logic?

 

Thanks a lot.

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Scholar
Scholar
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Registered: ‎04-07-2008

Re: Connecting the PLB to the user logic

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does you component need to hook up to the PLB bus.  Then I would create a IPIF and instantiate your component into the

IPIF user logic file.

 

If your component is independent of the PLB bus.  I would create a ISE project that contains your PPC system as a component.  Create a ISE top level file which instantiates your PPC system.  And then Instantiate your system in the

ISE Top Level file.  (where the PPC and the Component are at the same level hierarchly)

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Scholar
Scholar
4,831 Views
Registered: ‎04-07-2008

Re: Connecting the PLB to the user logic

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I was trying to edit my last reply but It does not change.

 

Even if you do not need to hook up to the PLB bus you can still instantiate your IPIF (staying within XPS) add a register even if you do not want to use it.  Instantiate your component within the IPIF User Logic File found in pcores directory.  Add your

other file in the hdl directory inside pcores directory.   Use the Peripheral tool to reimport all files plus your custom logic files

also.

 

 

 

 

I guess you can include your core directly into the MHS file.  I do not know how to do it that way however.  I think you

have to create a directory structure for the tool to find your core.

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Explorer
Explorer
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Registered: ‎11-06-2011

Re: Connecting the PLB to the user logic

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Hey.

 

I don't want to attach my logic to the bus.

 

I need to create an interface that is connected to the bus on one hand, and on the other hand, gives me the rd,wr,ale and add_data signals, that's what I need.

 

Thanks a lot.

 

Assaf.

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Explorer
Explorer
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Registered: ‎11-06-2011

Re: Connecting the PLB to the user logic

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So this is what I did so far.

 

I've created a simple IPIF with one register.

 

entity user_logic is
  generic
  (
    -- ADD USER GENERICS BELOW THIS LINE ---------------
    --USER generics added here
    -- ADD USER GENERICS ABOVE THIS LINE ---------------

    -- DO NOT EDIT BELOW THIS LINE ---------------------
    -- Bus protocol parameters, do not add to or delete
    C_SLV_DWIDTH                   : integer              := 32;
    C_NUM_REG                      : integer              := 1
    -- DO NOT EDIT ABOVE THIS LINE ---------------------
  );
  port
  (
    -- ADD USER PORTS BELOW THIS LINE ------------------
    slv_reg0_output                : out  std_logic_vector(0 to 31);
    -- ADD USER PORTS ABOVE THIS LINE ------------------

    -- DO NOT EDIT BELOW THIS LINE ---------------------
    -- Bus protocol ports, do not add to or delete
    Bus2IP_Clk                     : in  std_logic;
    Bus2IP_Reset                   : in  std_logic;
    Bus2IP_Data                    : in  std_logic_vector(0 to C_SLV_DWIDTH-1);
    Bus2IP_BE                      : in  std_logic_vector(0 to C_SLV_DWIDTH/8-1);
    Bus2IP_RdCE                    : in  std_logic_vector(0 to C_NUM_REG-1);
    Bus2IP_WrCE                    : in  std_logic_vector(0 to C_NUM_REG-1);
    IP2Bus_Data                    : out std_logic_vector(0 to C_SLV_DWIDTH-1);
    IP2Bus_RdAck                   : out std_logic;
    IP2Bus_WrAck                   : out std_logic;
    IP2Bus_Error                   : out std_logic
    -- DO NOT EDIT ABOVE THIS LINE ---------------------
  );

 

 

I want to connect that port to another interface I'll create in ISE which contain a fifo and also logic to give me all the other signals I'll need (rd, wr...).

 

The question is how?

How do I connect that port to a vhdl design I'll create in ISE?

Do I need to import my design to XPS?

 

Thanks a lot.

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Scholar
Scholar
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Registered: ‎04-07-2008

Re: Connecting the PLB to the user logic

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    -- ADD USER PORTS BELOW THIS LINE ------------------   

--  slv_reg0_output                : out  std_logic_vector(0 to 31);      Don't need to add these register outputs if you don't need 

-- the signals as outputs on the Processor system  -  Your PPC?MB can still use the register as a place to store data for

-- reading Add the ports you need here instead.

-- rst : IN  std_logic;

-- clk : IN  std_logic;  you may need or not need a external clock or reset       

add_data : INOUT  std_logic_vector(15 downto 0);         

ale : IN  std_logic;         

rd : IN  std_logic;         

wr : IN  std_logic;         

Rx_in : IN  std_logic_vector(1 downto 0);         

Tx_out : OUT  std_logic_vector(1 downto 0);         

msborlsb : IN  std_logic

 

 -- ADD USER PORTS ABOVE THIS LINE ------------------

 

 

Also Declare your component in this file.

 

And in the architecture section

 

Instantiate and wire up your component.

 

 

Finally Propagate your input and output signals to the next higher file also that hooks up to the PLB bus.

the Top level IPIF file.

 

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Explorer
Explorer
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Registered: ‎11-06-2011

Re: Connecting the PLB to the user logic

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Thanks.

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Observer
Observer
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Registered: ‎12-21-2011

Re: Connecting the PLB to the user logic

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Thanks!

 

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