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Observer s03311251
Registered: ‎08-07-2019

Data from PL to DDR4, how can PS know whether AXI transfer is completed?

  • I'm developing a project on a Zynq UltraScale+, which needs to:
  • Obtain data on PL side
  • Store the data obtained in DDR4 memory, that requires low latency and high thoughput (2.4GB/s to be exact)
  • Send the data to PC via USB3.0

Therefore, I've made a test program like this:



The my_data_generator above has a AXI-master interface, which puts some random data to HP0 on PS. I'm able to read data on DDR4 memory successfully from the PS program.

But I've got 2 questions:

  • How can PS know whether data from AXI slave is available on DDR4 memory, so that the USB transfer can be kick-started in my design? There's interrupt handler for XZdma, but it's for AXI Master on PS. Is there a similar thing for AXI Slave on PS?
  • Beside from the method I'm using, there are so many other ways to put data from PL to DDR4 (e.g. use AXI DMA, AXI CDMA, connect to PS's AXI Master and use XZdma on PS to queue DMA). What are their difference, and which one is the most suitable for my application that requires low latency and high thoughput?

Thank you.

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Xilinx Employee
Xilinx Employee
Registered: ‎10-04-2016

Re: Data from PL to DDR4, how can PS know whether AXI transfer is completed?

Hi @s03311251,

Generally speaking, it is up to your PL IP to let the PS know when there is data available for it to process. This is usually handled by the PL device signaling an interrupt to the processor.

You call out three different types of DMA IP. Here's what they are used for:

ZDMA : There are two instances of this in the ZUS+ PS. It is used for memory to memory transfers (read from one memory location, write to another location). Refer to Chapter 19 of UG1085.

CDMA : This is also a DMA for memory to memory transfers, but it is located in the PL. Refer to PG034.

AXI DMA: This DMA translates either streaming data into memory mapped data or memory mapped data into streaming data. Examples of IPs with streaming interfaces would be an ADC, DAC or AXI Ethernet. Refer to PG021.

I can't tell if any of the DMA IPs are helpful to you because I don't understand what the data source is for my_data_generator. They might be helpful examples of how to organize the register set for your IP so that it can interact with software.



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