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Visitor shrikanthym
Visitor
2,445 Views
Registered: ‎07-18-2017

Data transfer from PS(DDR) to PL using HP port on zcu102

Hi All,

 


I am transferring data from PS(DDR) to PL using HP port 1 ( AXI DMA). I am able to access control register which are memory mapped at address 0xAFFF8000. I am able to read back the default registers.

I am using following address map for data transfer memory mapped at address 0x20000000 (Address range 0x00000000 to 0x7FFFFFFF). I am not seeing any data at PL side.


I have gone through the below links and I have also followed the same  procedure.
https://forums.xilinx.com/t5/Zynq-All-Programmable-SoC/PS-and-PL-DDR-access-in-linux/td-p/725170


Any pointers on the same will be much appreciated.

 

dma_addressmap.png

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2 Replies
Xilinx Employee
Xilinx Employee
2,428 Views
Registered: ‎08-02-2011

Re: Data transfer from PS(DDR) to PL using HP port on zcu102

Can you post a screenshot of your block design and also an ILA capture of what you see at the output of the DMA (MM2S)?
www.xilinx.com
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Visitor shrikanthym
Visitor
2,364 Views
Registered: ‎07-18-2017

Re: Data transfer from PS(DDR) to PL using HP port on zcu102

Hi bwiec,

 

                Please find the screen shot for Block Design and Address Editor below.
                 

               Design is updated with two DMA's. One each for Transmit and Receive connecting to HP1 and HP2 respectively.
               
                When we trigger "m_axis_mm2s_tvalid" signal on Hardware manager, It is always in waiting mode.
                During Immediate Trigger, we can see "m_axis_mm2s_tready" is high and rest all signals are "0".
               
                Tool Used: VIVADO 2016.4address_map.png

ZCU102_BD_1.png

 

ZCU102_BD_2.png

 


The address 0xAFFF8000 is using for control path.

I configured control registers as: MM2S_DMACR to 0x3 (to Start DMA operations), MM2S_DMASR to 0x0 (Scatter gather disabled), MM2S_SA to 0x20000000 and MM2S_LENGTH to 0x200.

 

After configuring the control registers I am writing data to the memory mapped address: for MM2S 0x20000000, S2MM 0x40000000

 

And we are using following device tree entry for DMA transfer.
axi_dma_0: axidma@afff8000 {
        compatible = "xlnx,axi-dma-1.00.a";
        #dma-cells = <1>;
        reg = < 0x0 0xafff8000 0x0 0x10000 >;
        xlnx,addrwidth = <0x20>;
        clocks = <0x8 0x4>;
        clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk";
        interrupt-parent = <0x2>;
        interrupts = < 0 33 4  0 34 4>;
   };

    fpga_axi: fpga-axi@20000000 {
        compatible = "simple-bus";
        interrupt-parent = <0x2>;
        //interrupt-parent = <&gic>;
  xlnx,bus-width = <0x100>;
        #address-cells = <0x2>;
        #size-cells = <0x1>;
        clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk";
        ranges = <0 0 0 0 0xffffffff>;

        tx_dma: dma@20000000  {
            compatible = "xlnx,axi-dma-mm2s-channel";
            reg = <0x0 0x20000000 0x10000>;
            #dma-cells = <1>;
            interrupts = <0 108 0>;
            //clocks = <&clk100>;
            clocks = <0x8 0x4>;

            dma-channel {
                xlnx,datawidth = <0x20>;
                xlnx,genlock-mode = <0x0>;
                xlnx,include-dre = <0x0>;
            };
        };

        rx_dma: dma@40000000 {
            compatible = "xlnx,axi-dma-s2mm-channel";
            reg = <0x0 0x40000000 0x10000>;
            #dma-cells = <1>;
            interrupts = <0 109 0>;
            //clocks = <&clk100>;
            clocks = <0x8 0x4>;

            dma-channel {
                xlnx,datawidth = <0x20>;
                xlnx,genlock-mode = <0x0>;
                xlnx,include-dre = <0x0>;
            };
        };


   };

ps7_afi_0: ps7-afi@0xFD360000 {
               compatible = "xlnx,ps7-afi-1.00.a";
               reg = <0x0 0xfd360000 0x1000>;
   };

    ps7_afi_1: ps7-afi@0xFD370000 {
               compatible = "xlnx,ps7-afi-1.00.a";
               reg = <0x0 0xfd370000 0x1000>;
    };

    ps7_afi_2: ps7-afi@0xFD380000 {
               compatible = "xlnx,ps7-afi-1.00.a";
               reg = <0x0 0xfd380000 0x1000>;
    };

    ps7_afi_3: ps7-afi@0xFD390000 {
               compatible = "xlnx,ps7-afi-1.00.a";
               reg = <0x0 0xfd390000 0x1000>;
    };

    ps7_afi_4: ps7-afi@0xFD3A0000 {
               compatible = "xlnx,ps7-afi-1.00.a";
               reg = <0x0 0xfd3a0000 0x1000>;
    };

    ps7_afi_5: ps7-afi@0xFD3B0000 {
               compatible = "xlnx,ps7-afi-1.00.a";
               reg = <0x0 0xfd3b0000 0x1000>;
    };

 

Thanks

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