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Observer glenn.ramsey
Observer
10,565 Views
Registered: ‎02-02-2008

Debugging ppc440mc_ddr2

Hi. I have a project that uses the ppc440mc_ddr2 core to connect the powerpc to an external DDR2 component. Unfortunately, I am getting odd addressing issues where a single write will write to multiple memory locations. In attempting to debug this, I have found that going through the MIG will allow me to access a debug port giving me full access to the physical signals and even allow me to dynamically adjust IDELAY tap values, which is amazing. However, MIG does not generate a design that can be directly interfaced with the powerpc like the ppc440mc_ddr2 core. Searching through the documentation on the core, there appears to be no option to generate a debug port on the ppc440mc_ddr2 core and the DDR2 signals can not simply be connected to a Chipscope core.

 

I was wondering if anybody knew of a better way to go about debugging the DDR2 connection besides attempting to glue the output from the MIG to the powerpc.

 

Regards,

Glenn 

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18 Replies
Visitor pdabrowski
Visitor
10,059 Views
Registered: ‎03-19-2009

Re: Debugging ppc440mc_ddr2

Hey Glenn -- Did you ever manage to hack the debug port in into the ppc440mc_ddr2 core? I'm also trying to get a little more information while debugging this IP core. Thanks!

 

-Paul

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Observer glenn.ramsey
Observer
10,007 Views
Registered: ‎02-02-2008

Re: Debugging ppc440mc_ddr2

Hi Paul. Fortunately for me I realized I was running the DDR2 at too slow of a clock speed. Speeding it up solved my problem, so I never delved into hacking the debug port out of the IP. Best of luck!
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Highlighted
8,956 Views
Registered: ‎03-25-2010

Re: Debugging ppc440mc_ddr2

I'm curious about this as well. Any update on whether it is possible?

 

I'm having trouble getting the PPC to communicate with the memory and am wondering if its stuck in the initialization sequence somewhere. I've also not had any luck getting chipscope hooked up to monitor the DDR2 signals. Any suggestions?

 

Thanks,

bryan

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Xilinx Employee
Xilinx Employee
8,949 Views
Registered: ‎07-30-2007

Re: Debugging ppc440mc_ddr2

Working with multiple designs with issues like this, theres a few things to look at.

 

First sure all of the MIG-related UCF and MHS constraints are correct.  See a 11.2 or later datasheet, as I've rewritten the how-to sections of that correct. If you've changed your pinout, a new MIG UCF and potentially MHS parameter is necessary.

 

Pay special attention to the PPC440 CPU MHS parameters, as they depend on the memory controller settings.  C_PPC440MC_CONTROL, C_BANK_CONFLICT, C_ROW_CONFLICT are the important ones.  These will have new DRCs to generate error messages for poor choices in 12.1 and 12.2.

 

If still in v2, check the various *_BITS MHS parameters.  They need to match the various *_WIDTH parameters exactly, or things won't work. These are handled automatically in v3.00.a and later.

 

Check clock frequencies and the rest of the memory controller timing values.

 

Upgrade to v3.00.a in 11.4.

 

You've likely solved your problem by now. But if you've checked and double-checked the UCF and MHS parameters and suspect a memory interface problem, consider creating a MIG design to debug the physical parts of the interface, since there is more intrumentation that can be used.

0 Kudos
8,938 Views
Registered: ‎03-25-2010

Re: Debugging ppc440mc_ddr2

Thanks for the response. Which file are you referring to?

 

I went through ppc440mc_ddr2.pdf and setup those three constants according. However, that didn't seem to solve my problem. I'm sure my UCF is correct, not so confident in the MHS. (I've included the PPC440 and DDR2 blocks below)

 

I have not been able to generate a bitfile that has a chipscope module that monitors the DDR2 signals and I don't see any options for enabling debug ports on the ppc440mc. Any suggestions there? Is it possible to easily chipscope signals internal to the MC?

 

bryan

 

BEGIN ppc440_virtex5

PARAMETER INSTANCE = ppc440_0

PARAMETER C_IDCR_BASEADDR = 0b0000000000

PARAMETER C_IDCR_HIGHADDR = 0b0011111111

PARAMETER C_SPLB0_NUM_MPLB_ADDR_RNG = 0

PARAMETER C_SPLB1_NUM_MPLB_ADDR_RNG = 0

PARAMETER HW_VER = 1.01.a

PARAMETER C_PPC440MC_ROW_CONFLICT_MASK = 0x001FFF80

PARAMETER C_PPC440MC_BANK_CONFLICT_MASK = 0x0E000000

PARAMETER C_PPC440MC_CONTROL = 0xF8D0008F

BUS_INTERFACE MPLB = plb_v46_0

BUS_INTERFACE JTAGPPC = ppc440_0_jtagppc_bus

BUS_INTERFACE RESETPPC = ppc_reset_bus

BUS_INTERFACE PPC440MC = ppc440_0_PPC440MC

PORT CPMC440CLK = clk_400_0000MHzPLL0

PORT CPMINTERCONNECTCLK = clk_200_0000MHzPLL0

PORT CPMINTERCONNECTCLKNTO1 = net_vcc

PORT CPMMCCLK = clk_200_0000MHzPLL0_ADJUST

END

 

BEGIN ppc440mc_ddr2

PARAMETER INSTANCE = ddr2

PARAMETER HW_VER = 3.00.a

PARAMETER C_DDR_DWIDTH = 16

PARAMETER C_DDR_RAWIDTH = 13

PARAMETER C_DDR_BAWIDTH = 3

PARAMETER C_MEM_BASEADDR = 0x00000000

PARAMETER C_MEM_HIGHADDR = 0x07FFFFFF

PARAMETER C_DDR2_ODT_SETTING = 0

BUS_INTERFACE PPC440MC = ppc440_0_PPC440MC

PORT DDR2_DQ = DDR2_DQ

PORT DDR2_DQS = DDR2_DQS

PORT DDR2_DQS_N = DDR2_DQS_n

PORT DDR2_A = DDR2_Addr

PORT DDR2_BA = DDR2_BankAddr

PORT DDR2_RAS_N = DDR2_RAS_n

PORT DDR2_CAS_N = DDR2_CAS_n

PORT DDR2_WE_N = DDR2_WE_n

PORT DDR2_CS_N = DDR2_CS_n

PORT DDR2_ODT = DDR2_ODT

PORT DDR2_CKE = DDR2_CE

PORT DDR2_DM = DDR2_DM

PORT DDR2_CK = DDR2_Clk

PORT DDR2_CK_N = DDR2_Clk_n

PORT idelay_ctrl_rdy_i = net_vcc

PORT mc_mibclk = clk_200_0000MHzPLL0_ADJUST

PORT mi_mcclk90 = clk_200_0000MHzPLL0

PORT mi_mcclkdiv2 = clk_100_0000MHzPLL0_ADJUST

PORT mi_mcclk_200 = clk_200_0000MHzPLL0_ADJUST

PORT mi_mcreset = sys_bus_reset

END

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Xilinx Employee
Xilinx Employee
8,929 Views
Registered: ‎07-30-2007

Re: Debugging ppc440mc_ddr2

Since the default CA_WIDTH is 10, I get:

PARAMETER C_PPC440MC_ROW_CONFLICT_MASK = 0x000FFF80

PARAMETER C_PPC440MC_BANK_CONFLICT_MASK = 0x00700000

8,926 Views
Registered: ‎03-25-2010

Re: Debugging ppc440mc_ddr2

Thanks dylan. I agree with your numbers and see where I went wrong in my calculations. However, that still doesn't fix my problem.

 

I've noticed that I lose debug control of the PPC through XMD after trying a DDR2 memory access. I do a "rrd" in XMD and see that all registers have 0xF7FFEFEF, which is the same value that XMD reports for every DDR2 address I try to read. Any ideas?

 

bryan

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Xilinx Employee
Xilinx Employee
8,923 Views
Registered: ‎07-30-2007

Re: Debugging ppc440mc_ddr2

Is your memory clock and memory clock 90 phase aligned?

How are you sure that your UCF is OK?  What process did you follow to obtain it? Were any pins changed for layout purposes?

8,906 Views
Registered: ‎03-25-2010

Re: Debugging ppc440mc_ddr2

Hi dylan,

 

I did find a problem in the clock being used. I opened the clock block in xps and it found it automatically and corrected. That seemed to have improved things some, but I'm still not all the way there. Now, in XMD I do not lose registers after attempting ddr2 writes and doing a "rrd" shows that they are still ok. However, after doing a write I do a ddr2 read and I see the data I just tried to write being reported in every address. I've scoped the signals on the board going to the memory and they don't appear to be toggling for a write/read, so it must be reporting something left over on the plb.

 

When I scope the signals I see CS_L low for all time, WE_L toggles low every period, CAS_L toggles low every period, RAS_L toggles low a few times (3) every period. The ODT signal is low for all time. A period is 7.8us.

 

I went through MIG to generate the ucf. I then modified it according to "Using Custom MIG-Compatible Pinouts" section of ppc440mc_ddr2.pdf, except for steps 6 and 7. I tried setting those parameters in the mhs, but it errored out in xps. No pins were moved and I've used the defaults that MIG suggested.

 

Thanks again for the help. I feel like I'm getting a little closer.

-bryan

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Xilinx Employee
Xilinx Employee
7,816 Views
Registered: ‎07-30-2007

Re: Debugging ppc440mc_ddr2

There is no step 7 in that section. Could you be looking at the v2.00.c datasheet which had extra steps? It sounds like the memory controller is not finishing calibration.  You can check this by adding chipscope in EDK. Note that you might have to manually connect signals between the memory controller and the PPC440 block to be able to see them in the EDK chipscope signal viewer.  You are looking for READYTOACCEPT to go high at some point.

0 Kudos
7,813 Views
Registered: ‎03-25-2010

Re: Debugging ppc440mc_ddr2

I'm using the version on the xilinx website. Doc version 1.7, 6/24/09. Looks like version 2.00b. Is there a newer version elsewhere?

 

I'd love to try the Chipscope route, but there doesn't appear to be any debug signals available. Is there a way to turn these on? I only see the external signal that go to the off chip memory, none of the internal signals appear to be available.

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Xilinx Employee
Xilinx Employee
7,810 Views
Registered: ‎07-30-2007

Re: Debugging ppc440mc_ddr2

Yes, looks like the website for that doc is old.  I've filed a request to get it updated. Sorry about that.

  

If you open your design in EDK XPS, and then right-click on the core, you should be able to launch the datasheet.

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7,807 Views
Registered: ‎03-25-2010

Re: Debugging ppc440mc_ddr2

Good news! Looks like I'm able to read/write now. I'm sure there were many tweaks that ultimately made it work, but the final thing I did was manually define a bunch of the MHS Parameters for the PPC440MC_DDR2 block. I believe that C_DDR_DQS_WIDTH and C_DDR_DM_WIDTH were the two that made it work, but it could have been others. I'm not sure why EDK doesn't automatically assign those, nor is there any mention of needing to assign those in any of the documentation I reviewed (perhaps I missed it).

 

I've only done some preliminary testing, but the out-of-the box memory test that Xilinx provides reported all passes as did my manually reading and writing with the mrd/mrw commands in XMD.

 

Thanks for all your help dylan.

 

Here is my MHS for the PPC440 and DDR2 blocks if anyone is interested.

 

BEGIN ppc440_virtex5
 PARAMETER INSTANCE = ppc440_0
 PARAMETER C_IDCR_BASEADDR = 0b0000000000
 PARAMETER C_IDCR_HIGHADDR = 0b0011111111
 PARAMETER C_SPLB0_NUM_MPLB_ADDR_RNG = 0
 PARAMETER C_SPLB1_NUM_MPLB_ADDR_RNG = 0
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_PPC440MC_ROW_CONFLICT_MASK = 0x000FFF80
 PARAMETER C_PPC440MC_BANK_CONFLICT_MASK = 0x00700000
 PARAMETER C_PPC440MC_CONTROL = 0xF8D0008F
 PARAMETER C_PPC440MC_MAX_BURST = 8
 PARAMETER C_MPLB_MAX_BURST = 4
 BUS_INTERFACE MPLB = plb_v46_0
 BUS_INTERFACE JTAGPPC = ppc440_0_jtagppc_bus
 BUS_INTERFACE RESETPPC = ppc_reset_bus
 BUS_INTERFACE PPC440MC = ppc440_0_PPC440MC
 PORT CPMC440CLK = clk_400_0000MHzPLL0
 PORT CPMINTERCONNECTCLK = clk_200_0000MHzPLL0
 PORT CPMINTERCONNECTCLKNTO1 = net_vcc
 PORT CPMMCCLK = clk_200_0000MHzPLL0_ADJUST
END

 

BEGIN ppc440mc_ddr2
 PARAMETER INSTANCE = ddr2
 PARAMETER HW_VER = 3.00.a
 PARAMETER C_INCLUDE_ECC_SUPPORT = 0
 PARAMETER C_MIB_MC_CLOCK_RATIO = 1
 PARAMETER C_MC_MIBCLK_PERIOD_PS = 5000
 PARAMETER C_IDEL_HIGH_PERF = TRUE
 PARAMETER C_DDR_DWIDTH = 16
 PARAMETER C_DDR_RAWIDTH = 13
 PARAMETER C_DDR_BAWIDTH = 3
 PARAMETER C_DDR_DQS_WIDTH = 2
 PARAMETER C_DDR_DM_WIDTH = 2
 PARAMETER C_MEM_BASEADDR = 0x00000000
 PARAMETER C_MEM_HIGHADDR = 0x07FFFFFF
 PARAMETER C_DDR_TWTR = 7500
 PARAMETER C_DDR_TRFC = 127500
 PARAMETER C_DDR_TREFI = 3900
 PARAMETER C_DDR_CAS_LAT = 4
 PARAMETER C_DDR2_ODT_SETTING = 3
 PARAMETER C_DDR_BURST_LENGTH = 4
 PARAMETER C_NUM_IDELAYCTRL = 1
 PARAMETER C_SIM_ONLY = 0
 PARAMETER C_DQ_BITS = 4
 PARAMETER C_DQS_BITS = 1
# PARAMETER C_DQS_IO_COL = 0b0000
# PARAMETER C_DQ_IO_MS = 0b1010101011010101
 BUS_INTERFACE PPC440MC = ppc440_0_PPC440MC
 PORT DDR2_DQ = DDR2_DQ
 PORT DDR2_DQS = DDR2_DQS
 PORT DDR2_DQS_N = DDR2_DQS_n
 PORT DDR2_A = DDR2_Addr
 PORT DDR2_BA = DDR2_BankAddr
 PORT DDR2_RAS_N = DDR2_RAS_n
 PORT DDR2_CAS_N = DDR2_CAS_n
 PORT DDR2_WE_N = DDR2_WE_n
 PORT DDR2_CS_N = DDR2_CS_n
 PORT DDR2_ODT = DDR2_ODT
 PORT DDR2_CKE = DDR2_CE
 PORT DDR2_DM = DDR2_DM
 PORT DDR2_CK = DDR2_Clk
 PORT DDR2_CK_N = DDR2_Clk_n
 PORT idelay_ctrl_rdy_i = net_vcc
 PORT mc_mibclk = clk_200_0000MHzPLL0_ADJUST
 PORT mi_mcclk90 = clk_200_0000MHz90PLL0_ADJUST
 PORT mi_mcclkdiv2 = clk_100_0000MHzPLL0_ADJUST
 PORT mi_mcclk_200 = clk_200_0000MHzPLL0
 PORT mi_mcreset = sys_bus_reset
END

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Xilinx Employee
Xilinx Employee
7,805 Views
Registered: ‎07-30-2007

Re: Debugging ppc440mc_ddr2

Good to hear.  Yes, you need to specify the _WIDTH parameters.

 In v3.00.a the _BITS parameters no longer needed to be checked. 12.1 will also check the PPC440 C_PPC440MC_CONTROL, and just submittted some code for 12.2 that will also check the C_ROW/BANK_CONFLICT_MASK parameters.

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Observer c.gianni
Observer
7,434 Views
Registered: ‎03-01-2010

Re: Debugging ppc440mc_ddr2

Hi, I have a problem to with my custom board with Virtex 5 FX130T on it. I use the ppc440mc_ddr2 to drive a ddr2 memory from micron: mt4764m16 1Gbit.

 

The problem is that when I try to write and read from memory, even from XMD I manage to read and write only the first four bytes every sixteen bytes, it is like it can't access certain locations of memory, I think that the problem is behind the configuration with MHS, but I can't understand where, could you help me?

 

This is the odd thing I got after writing the byte 0x55 in every location of the memory:

 

 XMD% mrd 00000000 10 1
       0:   55555555
       4:   00000000
       8:   00000000
       C:   00000000
      10:   55555555
      14:   00000000
      18:   00000000
      1C:   00000000
      20:   55555555
      24:   00000000

 

And these are my MHS settings:

 

BEGIN ppc440_virtex5
 PARAMETER INSTANCE = ppc440_0
 PARAMETER C_IDCR_BASEADDR = 0b0000000000
 PARAMETER C_IDCR_HIGHADDR = 0b0011111111
 PARAMETER C_PPC440MC_ROW_CONFLICT_MASK = 0x000FFF80
 PARAMETER C_PPC440MC_BANK_CONFLICT_MASK = 0x00700000
 PARAMETER C_PPC440MC_CONTROL = 0xF8D0008F
 PARAMETER C_SPLB0_NUM_MPLB_ADDR_RNG = 0
 PARAMETER C_SPLB1_NUM_MPLB_ADDR_RNG = 0
 PARAMETER HW_VER = 1.01.a
 BUS_INTERFACE MPLB = plb_v46_0
 BUS_INTERFACE PPC440MC = ppc440_0_PPC440MC
 BUS_INTERFACE JTAGPPC = ppc440_0_jtagppc_bus
 BUS_INTERFACE RESETPPC = ppc_reset_bus
 PORT CPMC440CLK = clk_400_0000MHzPLL0
 PORT CPMINTERCONNECTCLK = clk_200_0000MHzPLL0
 PORT CPMINTERCONNECTCLKNTO1 = net_vcc
 PORT CPMMCCLK = clk_200_0000MHzPLL0_ADJUST
END


BEGIN ppc440mc_ddr2
 PARAMETER INSTANCE = DDR2_SDRAM_W1D32M72R8A_5A
 PARAMETER C_INCLUDE_ECC_SUPPORT = 0
 PARAMETER C_DDR_BURST_LENGTH = 4
 PARAMETER C_MIB_MC_CLOCK_RATIO = 1
 PARAMETER C_IDEL_HIGH_PERF = TRUE
 PARAMETER HW_VER = 3.00.a
 PARAMETER C_DDR_TWTR = 7500
 PARAMETER C_DDR_TRAS = 70000
 PARAMETER C_DDR_TRFC = 127500
 PARAMETER C_DDR_DWIDTH = 16
 PARAMETER C_DDR_RAWIDTH = 13
 PARAMETER C_DDR_BAWIDTH = 3
 PARAMETER C_MC_MIBCLK_PERIOD_PS = 5000
 PARAMETER C_MEM_BASEADDR = 0x00000000
 PARAMETER C_MEM_HIGHADDR = 0x07FFFFFF
 PARAMETER C_DDR2_ADDT_LAT = 0
 PARAMETER C_NUM_IDELAYCTRL = 1
 PARAMETER C_DDR2_ODT_SETTING = 3
 BUS_INTERFACE PPC440MC = ppc440_0_PPC440MC
 PORT mc_mibclk = clk_200_0000MHzPLL0_ADJUST
 PORT mi_mcclk90 = clk_200_0000MHz90PLL0_ADJUST
 PORT mi_mcreset = sys_bus_reset
 PORT mi_mcclkdiv2 = clk_100_0000MHzPLL0_ADJUST
 PORT mi_mcclk_200 = clk_200_0000MHzPLL0
 PORT DDR2_DQ = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_DQ_pin
 PORT DDR2_DQS = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_DQS_pin
 PORT DDR2_DQS_N = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_DQS_N_pin
 PORT DDR2_A = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_A_pin_vslice_12_0_concat
 PORT DDR2_BA = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_BA_pin
 PORT DDR2_RAS_N = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_RAS_N_pin
 PORT DDR2_CAS_N = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_CAS_N_pin
 PORT DDR2_WE_N = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_WE_N_pin
 PORT DDR2_CS_N = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_CS_N_pin
 PORT DDR2_ODT = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_ODT_pin
 PORT DDR2_CKE = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_CKE_pin
 PORT DDR2_DM = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_DM_pin
 PORT DDR2_CK = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_CK_pin
 PORT DDR2_CK_N = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_CK_N_pin
END

 

 

 

 

 

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Xilinx Employee
Xilinx Employee
7,428 Views
Registered: ‎07-30-2007

Re: Debugging ppc440mc_ddr2

The repeated values usually mean the processor is hung.

 

What do you mean you received errors while filing the MIG directions?  Those UCF/parameters are critical to operation.

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Observer c.gianni
Observer
7,351 Views
Registered: ‎03-01-2010

Re: Debugging ppc440mc_ddr2

Hi, at the end I managed to make the controller work.. All that I have done has been taking the MHS settings on this thread and substituting it to mine.

However it is very odd that the auto generated MHS is working so bad..

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Xilinx Employee
Xilinx Employee
7,347 Views
Registered: ‎07-30-2007

Re: Debugging ppc440mc_ddr2

Good to hear.  In newer versions of the core, there are additional DRCs to set many of the parameters.  The user is still responsible for setting some of the memory parameters though.

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