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Registered: ‎11-21-2014

Example design for AXI4 Stream IP

Hi. Could anybody provide link, resource for example design for creating AXI4 stream (slave and Master) IP in Vivado? It looks like there are not enough good resources for learning and creating those.


I would like to create something like color filter interpolation or test pattern generator or chroma resampler or rgb to YUV or other AXI4 stream compliant IP. All IPs I mentioned before are encrypted RTL. I could not get to understand how they are made.


Please help how to design AXI 4 stream IP?


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4 Replies
Scholar austin
Registered: ‎02-27-2008

Re: Example design for AXI4 Stream IP

The demonstration design is an AXI stream video application:




Also available for zedboard, ZC706 board, and others.



Austin Lesea
Principal Engineer
Xilinx San Jose
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Registered: ‎11-21-2014

Re: Example design for AXI4 Stream IP

@austin Hello sir. I have already checked this design. I am not talking about the IP integration in Vivado which I also followed in Xapp 1167. My question is how to design one of the IPs like cfa, gamma correction, rgb to yuv, etc. i.e I would like to create IP similar to them(with input axi4 stream slave and output axi4 stream master). So, I am looking for a example design or link or resource to help me do this.


Thanks for your help though.

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Visitor mdvankar1990
Registered: ‎08-09-2017

Re: Example design for AXI4 Stream IP

I am working on zc702 board and in it I don't know how to create custom ip.
but I saw some info on it.
check out chapter 7 of above link
hope it will be helpful
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Visitor nickthequik
Registered: ‎10-15-2017

Re: Example design for AXI4 Stream IP

In Vivado, navigate to the Tools -> Create and Package IP option. A window that looks something like the screencap below will pop up.



Select Create a new AXI4 peripheral and then click next. A new menu will pop up to name the IP block and save it to a project directory. Name it what you want then click next. Another menu like the one below will open.


Here you can add AXI interfaces and choose whether they are master or slave. I have added an AXI-Stream Slave and AXI-Stream Master.


After you hit next and "Edit IP" in the next menu, it will take you to the Vivado project where you can actually write the HDL for the IP block. It seems like you will have to write everything including the AXI-Stream state machine. It would be nice if they provided this, but the AXI-Stream protocol is not that complicated to implement.


I am still fairly new to this process as well. One thing I noticed is that the data input and output widths are locked at 32 with no other options. I found I was able to change this in the Customization Parameters menu in the Package IP Window.

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