09-06-2019 07:14 AM
I am using Vivado 2019.1 and a Zynq Ultrascale+ SoC.
How can I verify that a given MIO is routed to a specific package pin?
I recustomized my PS to have GPIO set up to use a range of MIO, and I see that my package pins in the Implementation flow are (apparently) correctly assigned to the port names from my block design.
But I don't see where the MIO range explictly links my block design ports to package pin numbers. Does Vivado do this automatically, and is there some way I can verify that the assignments are correct? If it's not automatic, how to I make these assignments?
09-30-2019 02:20 AM
09-30-2019 03:08 AM
When you defined the SOC capabilities,
you selected which pin to use on that package.
its fixed, but flexible in the spftware. i.e. a particular pin could be MIO or say a MOSI pin...
chapter 27 and 28
what you then need is the ascii pin tables, chapter 3
Find your device / package , and yo have a link to the ascii table of that device.
for instance this file
and you will see for instance
so the MIO 0 is on pin AG15,
and the functoin of MIO 0 is defined in your software
There HAS to be a simpler way than this,
but I've only done this a few times, and htis way works for me, so I stick with it when I make the schematic symbols.
10-14-2019 02:37 PM
MIO assignments of Zynq Ultrascale devices are beyond automatic: they're fixed. They cannot be changed.
For a given die in a given package, 1 MIO goes to 1 pin. That's it. It doesn't go anywhere else.
Here's a completely arbitrary example.
Compare this listing from https://www.xilinx.com/support/packagefiles/zuppackages/xczu4cgsfvc784pkg.txt :
To the package diagram from UG1075: