cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
18,316 Views
Registered: ‎11-03-2011

How to access DDR memory with Custom IP using AXI bus?

I have a Microblaze based design which uses the AXI bus for peripheral interconnect and an axi_s6_ddrx memory controller. The Microblaze can read/write to DDR (memory test passed on my hardware) so the embedded system is working.  However, now  would like to have my custom IP module (which is reading from an external high-speed A/D chip) dump the data directly to the DDR.  How do I interface my custom IP to the DDR?  Implement a master AXI controller in VHDL and use port 2 on the axi_s6_ddrx?

 

Or should I use some other method than AXI bus??

 

FPGA: Spartan 6 XC6SLX25

Memory: LPDDR chip

 

17 Replies
Highlighted
Teacher
Teacher
18,309 Views
Registered: ‎09-09-2010

Re: How to access DDR memory with Custom IP using AXI bus?

Does the Microblaze need to see the A/D data on the way to the DDR memory?
Does the Microblaze need to access the DDR memory for other reasons?

------------------------------------------
"If it don't work in simulation, it won't work on the board."
0 Kudos
Highlighted
Visitor
Visitor
18,299 Views
Registered: ‎11-03-2011

Re: How to access DDR memory with Custom IP using AXI bus?

The goal is to:
1) stream a block of the high sped data directly from the A/D to the DDR using my custom IP (while the microblaze waits)
2) then have the microblaze read the data from the DDR, do some processing and send it out a UART line to a terminal.

I have the microblaze to DDR path working great and I can read/write test patterns and dump stuff out the UART. Just can't seem to figure out the best way for the custom IP to write to DDR.
0 Kudos
Highlighted
Adventurer
Adventurer
18,228 Views
Registered: ‎09-02-2010

Re: How to access DDR memory with Custom IP using AXI bus?

Hi dshine, I am trying to do something pretty similar. I have many ADCs generating data and I want to store it into my DDR3 through the Spartan6's MCB straight away withough passing through the MicroBlaze and then using the MicroBlaze to send the data over ethernet using axi_ethernetlite core.

 

How did you do it in the end? I guess a master AXI4 peripheral has to be created so that burst write operations can be performed to the MCB (so that a high speed can be achieved). I have found the vhdl and mpd files describing the interface with the AXI bus in http://www.xilinx.com/support/answers/37425.htm or using CIP should be possible too (I am not 100% sure as I am away from EDK now) but my problem is how to design the internals of my IP Peripheral so that it can write to certain address on the AXI bus... I mean, should I just get the specification of the AXI4 bus and desing my hardware to produce the required timmings or is there an easier way to do this?

 

 

Any help will be appreciated! ;)

 

Thanks.

Highlighted
Adventurer
Adventurer
18,201 Views
Registered: ‎09-02-2010

Re: How to access DDR memory with Custom IP using AXI bus?

Anyone?? Is what I am saying even possible? I have not found the way to create a master AXI4 peripheral that can write directly to the MCB using an AXI4 port...

Highlighted
Newbie
Newbie
17,382 Views
Registered: ‎01-28-2013

Re: How to access DDR memory with Custom IP using AXI bus?

I am trying to do the same thing. I wonder if you have found the solution.

0 Kudos
Highlighted
Explorer
Explorer
17,265 Views
Registered: ‎12-01-2010

Re: How to access DDR memory with Custom IP using AXI bus?

I am also attempting to do this!  What are the basic steps to this?  A dual port memory controller? An external AXI master? Is there an example project for the 7 series somewhere?

0 Kudos
Explorer
Explorer
17,161 Views
Registered: ‎12-01-2010

Re: How to access DDR memory with Custom IP using AXI bus?

Just to close the loop on this, a master can be made relatively easily.

 

What you need to do is create an AXI_master IP.  This IP will then share master control with the MB over the DDR memory, which is the slave peripheral on the bus.

 

(taken from UG761 - AXI Reference Guide)

 

 

To do this, open XPS

run  Hardware->Create or import peripheral

Choose AXI4.  For the KC705, the projects all have the DDR3 located as a slave on an AXI4 bus.

Make sure to check the box "User Logic Master Support"

 

This will generate an IP with two files inside:  a top level (same name as your IP) and a user_logic.vhd

The User logic is a fully functional AXI_master that comes generated with a simple test program to exercise read and writes as an AXI master.

 

Once it is made, add the IP to your design, and connect M_AXI bus to the same bus as your DD3 memory.

 

 

Give it an address and you're set to go.  Implement your design.

 

You execute reads & writes by writing to the slave register of the IP to set parameters, and the IP takes care of the rest. 

This is easily done through the XMD console.

 

All the details you need can be found in the generated user_logic.vhd file.

 

 One thing to note (this gave me some trouble) is that there is a FIFO in the IP.  The IP writes FROM the FIFO to the AXI bus.  But it needs to have something in it, or it will writes zeroes.  So you need to do some AXI master reads of locations first to fill it up.

 

Once you've got the basics down of how it works, you are free to modify the user_logic file to do what you need it to do.

0 Kudos
Highlighted
Explorer
Explorer
17,068 Views
Registered: ‎12-01-2010

Re: How to access DDR memory with Custom IP using AXI bus?

Update!

I have recently spend considerable time debugging an AXI master design.  The problem presented itself as a strange burst write data timing issue, coupled with the state machine not receiving the AXI done signal, preventing future writes. I've discovered a solution to the problem, and it's described below

The Master writer VHDL i am using is a modified version originally generated by XPS Create or Import Peripheral Wizard. (As specified in the previous post)  This generated an AXI top level wrapper and a user_logic file.  Simulating the user_logic by itself never presented a problem.  However, when simulating the AXI top level wrapper, you need two frequencies: one for the AXI_master and one for the AXI_slave.  Normally, they are set the same, and everything works.  However, if you set these two frequencies to a different value, the design breaks!  The problem is that the user_logic is generated with only the slave clock from the top level.  This causes all reads & writes generated by the user_logic to be tied to the incorrect (and usually slower) clock.  The solution is to propagate BOTH clocks down to the user_logic file.  This is something the Wizard absolutely should do, but does not.  This requires modifying both the top_level and the user_logic. Then, inside the user_logic, the registers sit on the slave bus frequency (100 MHz in my case) and all other logic, state machines, etc runs off of the AXI-4 master frequency (150 MHz in my case).
Once this was done, the issue was immediately fixed, and the IP works flawlessly.

The bottom line is that the CIP Wizard (for all versions 14.5 and before) generates a design that WILL NOT WORK for any system with different clock speeds on the master & slave busses.  This specifically includes the KC705 reference design.  There appears to be no issue when the frequencies are the same.

0 Kudos
Highlighted
Adventurer
Adventurer
17,044 Views
Registered: ‎04-07-2011

Re: How to access DDR memory with Custom IP using AXI bus?

hi markzak

 

Well your info was quite informative but I have  a doubt, if we connect the s_axi and the m_axi to two different interconnects ie the s_Axi to the axi lite interconnect and the M_AXI to the axi 4 interconnect , in that case the two clocks would be different automatically, would  the template created in the top level not give two different clocks?

 

If not, in that case you mean to say you tokk the master frequency clock (which I assume is not  the axi lite interface clock)and take it as a port in the entity declaraion of the top level created in the hierarchy which is then port mapped in the user logic.vhd. Please correct me if I am wrong.

 

Ok you have also mentioned that you have simulated the custom ip core. did u do tht in the edk environment or in the ISE environment ????

 

 

Look forward to your reply.

 

akanksha

 

0 Kudos
Highlighted
Explorer
Explorer
9,591 Views
Registered: ‎12-01-2010

Re: How to access DDR memory with Custom IP using AXI bus?

akanksha,

    That is the main problem that i described.  The CIP Wizard includes both clocks, but only in the top level wrapper.  The generated  user_logic only includes the slave clock interface in the template.  The CIP Wizard has no idea how you plan on connecting your clocks later on, and assumes they are the same frequency.

    Yes.  The solution is to modify the top level AXI by adding the m_axi_aclk in the ports of the user_logic instantiation.  Then, in the user_logic, adding this clock to the ports entity declaration.  Remember, this master clock drives all logic and state machines inside the user_logic, with the exception of the master/slave registers.  They are accessed through the AXI_lite, and hence remain on the original slave clock.

 

I simulated the entire AXI top level through ISE, in a separately created project.  This is much faster than simulating the entire system!    When you create your original template with the CIP Wizard, make sure to check the box that creates a project for you.  This will associate all libraries for you, and make testing a breeze.

 

I've attached the testbench i used to simulate the top_level.  It will need to be modified to suit your specific code, but it works fine responding to AXI writes generated by your IP.

0 Kudos
Highlighted
Adventurer
Adventurer
9,579 Views
Registered: ‎04-07-2011

Re: How to access DDR memory with Custom IP using AXI bus?

Heya

Thanks so much for replying. I got your points.

 

Ok now while i was ading the custom IP to my EDk design, I faced a few issues. Since you have already done a similar design, I thought you would be bale to drop hints about the same.

 

My custom IP is such that it has some read write registers interacting with the microblaze over the AXI Lite bus.

 

Now apart from this I want my custom IP to have two master AXI ports to write two different set of values through the AXI interconnect to the DDR.

 

The problems , I am facing are

 

1. If after creating the custom IP through the create /import peripheral, and selecting the user master logic too. I later import the peripheral, finally the gui where we need to select the bus interface type, I need both master and slave ports to be enabled. Now ober there, I could select AXI lite as either master or a  slave port but I want my CUSTOM IP to interact with the Ublaze over the S_AXI and write to the DDR over the M_AXI and both of them being AXI LITE interfaces.

 

Now the GUI does not allow me to select M_AXI and S_AXI bothe on AXI Lite interface. How do I tackle this problem? Does the M_AXI port need to be done manually by adding the port names in the USER logic and then port mapping it?

 

2. I want to have two M_AXI ports for my cstom IP both writing to the DDR . How do I do this ?

 

3. Once i have added these ports, (assuming I do it manually), How do I connect them to the DDR. I mean how do I bundle them together such that it means only one connetion like M_AXI which then could be ported to DDR3 memory bus. I read that we can do that b defining the bus interface type in the .mpd file.But I am not too sure of it. I would anyways explore it, but if you have already done it, maybe you could suggest me the exact way of doing it.

 

Really looking forward to your reply.

 

akanksha

 

0 Kudos
Highlighted
Explorer
Explorer
9,565 Views
Registered: ‎12-01-2010

Re: How to access DDR memory with Custom IP using AXI bus?

Akanksha,

  I think we are getting into the specifics of your design here.  I have based my design off of the KC705 base design.  This design has two AXI-4 busses and an AXI-lite bus.  See message #8 in this thread on how to connect them to the IP in XPS.

  As far as having two Master AXI ports on one IP, i think that's a bad idea.  You are going to cause bus fights from the same interface, not to mention greatly complicate your design.  If you want to have multiple data streams you need to create that logic inside the user_logic.  Think of it as a mux, where you either are writing from one source to the DDR or the other.  You can't write both at the same time even if you wanted, as DDR is a single port memory.  An alternative would be to make two completley seperate IPs.

Highlighted
Adventurer
Adventurer
9,547 Views
Registered: ‎04-07-2011

Re: How to access DDR memory with Custom IP using AXI bus?

Hi Markzak

Thanks for reverting.

 

M elaborating my doubts inline to your pointers.

 

  I think we are getting into the specifics of your design here.  I have based my design off of the KC705 base design.  This design has two AXI-4 busses and an AXI-lite bus.  See message #8 in this thread on how to connect them to the IP in XPS.

 

I saw  message 8 and I wanted to confirm a few things, from what I could gather, the external master connecttor would be useful if we need to use edk as a component i the project navigator and axi master is outside the edk flow , maybe as another submodule in the top level and wht we would do is port map the axi master signals to the edk top level ports which in turn are AXI master connector signals. Correct me if I am wrong.

 

  As far as having two Master AXI ports on one IP, i think that's a bad idea.  You are going to cause bus fights from the same interface, not to mention greatly complicate your design. 

I actually need two AXI Read Masters, to read two different chunk of values from the DDR at different addr ranges so it would be like two AXI Read Masters reading from different set of locations. would this too cause a problem?

 

If you want to have multiple data streams you need to create that logic inside the user_logic.  Think of it as a mux, where you either are writing from one source to the DDR or the other.  You can't write both at the same time even if you wanted, as DDR is a single port memory.  An alternative would be to make two completley seperate IPs.

 

 

 

Can I modify the .mpd file to add the two ports as I do not want xternal master connector (fromw ht I could gather as i ahve mentioned above), I would be having EDK as the Top level.

 

 

Please reply.

 

 

 

 

 

 

 

 

 

Highlighted
Explorer
Explorer
9,524 Views
Registered: ‎12-01-2010

Re: How to access DDR memory with Custom IP using AXI bus?

Akanksha,
    The AXI master (whether read or write) does not get assigned an address range.  Only the slave portion does, to allow the MB to access registers specifically.  The AXI master can access all memory ranges, with a caveat.  The AXI master is a master of something.  The usual case is DDR memory.  It is this DDR that is assigned a memory range.  The AXI master can access this entire range.
    So if you have one DDR3 memory, and are attempting to access two (or more) completely separate portions of this memory for either read or write, you still only need one AXI master to do this, since it can access the entire slave memory range.  The specific addressing for the reads needs to be done in the the user_logic.vhd file.  And since you can physically read only one address at a time, you will have to mux the access to the memory.
    If you are still hell-bent on having two master ports in one IP, i can't help you as i have never done this.

0 Kudos
Highlighted
Participant
Participant
8,349 Views
Registered: ‎02-06-2013

Re: How to access DDR memory with Custom IP using AXI bus?

Hi markzak,

i know that is a long time that you post this Info, but can you send me please your top.vhd und user_logic.vhd or give me more info on this problem? I have exact the same problem now, the cmplt_flag doesn't come from time to time.

Many thanks

Abderrahim

0 Kudos
Highlighted
Visitor
Visitor
3,738 Views
Registered: ‎04-01-2018

Re: How to access DDR memory with Custom IP using AXI bus?

can you tell where to modify in user_logic

I am new to this 

 

Thank you

0 Kudos
Highlighted
Visitor
Visitor
2,621 Views
Registered: ‎11-26-2018

Re: How to access DDR memory with Custom IP using AXI bus?

User logic in a custom ip you created?
0 Kudos